CMU-SAFARI / rowhammerLinks
Source code for testing the Row Hammer error mechanism in DRAM devices. Described in the ISCA 2014 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf.
☆228Updated 10 years ago
Alternatives and similar repositories for rowhammer
Users that are interested in rowhammer are comparing it to the libraries listed below
Sorting:
- This repository contains examples of DRAMA reverse-engineering and side-channel attacks☆190Updated 8 years ago
- PTLsim and QEMU based Computer Architecture Research Simulator☆130Updated 3 years ago
- This repository contains examples of Flush+Flush cache attacks☆167Updated 4 years ago
- ☆19Updated 5 years ago
- Tools to track memory accesses in applications and visualize the patterns to reveal opportunities for optimization.☆92Updated 10 years ago
- ☆152Updated 7 years ago
- This repository contains several tools to perform Cache Template Attacks☆157Updated 2 weeks ago
- ☆195Updated last year
- TRRespass☆125Updated 4 years ago
- Minimal RISC Extensions for Isolated Execution☆53Updated 6 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- A wrapper for the SPEC CPU2006 benchmark suite.☆89Updated 4 years ago
- Tool for testing and finding minimal eviction sets☆105Updated 4 years ago
- This repository contains tools to perform modern cache attacks on ARM.☆292Updated 3 years ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆65Updated 6 years ago
- Website and PoC collection for transient execution attacks☆189Updated last year
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆138Updated 2 years ago
- Buffer overflow testbed, research paper published at ACSAC 2011☆91Updated 8 years ago
- Source code of the paper "Lord of the Ring(s): Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practical"☆144Updated 4 years ago
- ☆36Updated 6 years ago
- Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…☆50Updated 6 years ago
- tools for setting and accessing advaned low-level CPU features☆134Updated 2 years ago
- Microscope: Enabling Microarchitectural Replay Attacks☆20Updated 5 years ago
- A (Py)thon (D)SL for (G)enerating (In)struction set simulators.☆167Updated 7 years ago
- This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.☆23Updated last year
- A port of the RIPE suite to RISC-V.☆29Updated 7 years ago
- New Cache implementation using Gem5☆13Updated 11 years ago
- Creating beautiful gem5 simulations☆49Updated 4 years ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆20Updated 4 years ago
- ☆35Updated 4 years ago