Alternatives and similar repositories for pfloat

Users that are interested in pfloat are comparing it to the libraries listed below

• harvard-acc / EdgeBERT
  HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference
  ☆48Updated last year
• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆87Updated 2 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 3 months ago
• microideax / T-DLA
  ☆19Updated 5 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆52Updated last month
• ehw-fit / tf-approximate
  Approximate layers - TensorFlow extension
  ☆27Updated last month
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆30Updated 2 years ago
• zhutmost / neuralzip
  A Out-of-box PyTorch Scaffold for Neural Network Quantization-Aware-Training (QAT) Research. Website: https://github.com/zhutmost/neuralz…
  ☆26Updated 2 years ago
• PannenetsF / TQT
  TQT's pytorch implementation.
  ☆21Updated 3 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• nycu-caslab / TinyTS
  This is the open-source version of TinyTS. The code is dirty so far. We may clean the code in the future.
  ☆17Updated 10 months ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆19Updated 5 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆36Updated 5 years ago
• jafermarq / WinogradAwareNets
  Official implementation of "Searching for Winograd-aware Quantized Networks" (MLSys'20)
  ☆27Updated last year
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆29Updated 3 years ago
• zeasa / nvdla-compiler
  ☆44Updated 5 years ago
• hisrg / Neural-Network-Compression-and-Accelerator-on-Hardware
  My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, …
  ☆51Updated 2 years ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆47Updated 3 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆33Updated 5 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆36Updated 4 years ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• da-steve101 / binary_connect_cifar
  An implementation of a BinaryConnect network for cifar10
  ☆11Updated 5 years ago
• union-codesign / union
  ☆14Updated 3 years ago
• he-actlab / polymath
  ☆21Updated 3 months ago
• pulp-platform / pulp-nn
  ☆81Updated last year
• Xilinx / pyxir
  ☆37Updated 3 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆39Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• BoyuanFeng / APNN-TC
  ☆17Updated 3 years ago