AmiraGuesmi-mls / Defensive-Approximation
Implementation of our proposed defense strategy against adversarial attacks "Defensive Approximation (DA)"
☆8Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for Defensive-Approximation
- Heterogenous ML accelerator☆16Updated last month
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆17Updated 8 months ago
- ☆22Updated last year
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆22Updated 2 years ago
- ☆13Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- ☆25Updated 3 years ago
- A general framework for optimizing DNN dataflow on systolic array☆33Updated 3 years ago
- Open-source artifacts and codes of our MICRO'23 paper titled “Sparse-DySta: Sparsity-Aware Dynamic and Static Scheduling for Sparse Multi…☆32Updated last year
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆29Updated 2 years ago
- ☆15Updated last year
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆15Updated 2 years ago
- ☆10Updated last year
- Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices☆12Updated 3 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago
- first-order deep learning accelerator model☆18Updated 6 years ago
- ☆31Updated 3 years ago
- ☆10Updated last month
- ☆20Updated 2 years ago
- Computational Memory Neural Network Compiler☆10Updated 3 years ago
- ☆16Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆46Updated 2 weeks ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆12Updated 2 years ago
- ☆12Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆30Updated last month
- HWASim is a simulator for heterogeneous systems with CPUs and Hardware Accelerators (HWAs). It is released with the DASH memory scheduler…☆17Updated 8 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 3 years ago
- ☆12Updated 11 months ago
- ☆24Updated 7 months ago