AmiraGuesmi-mls / Defensive-Approximation
Implementation of our proposed defense strategy against adversarial attacks "Defensive Approximation (DA)"
☆8Updated 3 years ago
Alternatives and similar repositories for Defensive-Approximation
Users that are interested in Defensive-Approximation are comparing it to the libraries listed below
Sorting:
- ☆11Updated 9 months ago
- Pytorch implementation of Bit-Flip based adversarial weight Attack (BFA)☆32Updated 3 years ago
- Implementation of Input Stationary, Weight Stationary and Output Stationary dataflow for given neural network on a tiled architecture☆9Updated 5 years ago
- Heterogenous ML accelerator☆18Updated last week
- Computational Memory Neural Network Compiler☆11Updated 3 years ago
- first-order deep learning accelerator model☆18Updated 7 years ago
- ☆25Updated 3 years ago
- ☆13Updated 4 years ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆15Updated 3 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- ☆26Updated last year
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆23Updated 2 years ago
- ☆8Updated 2 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Updated 6 years ago
- Approximate layers - TensorFlow extension☆27Updated last month
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆22Updated last year
- A general framework for optimizing DNN dataflow on systolic array☆35Updated 4 years ago
- ☆70Updated 5 years ago
- ☆13Updated last year
- ☆28Updated 2 years ago
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆13Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 3 years ago
- ☆12Updated 3 years ago
- ☆29Updated 6 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆35Updated 3 weeks ago
- ☆10Updated 7 months ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆11Updated last year