Adrofier / HDLBits-Verilog-SolutionsLinks
Solutions to HDLBits Verilog Problem Set
☆36Updated 4 months ago
Alternatives and similar repositories for HDLBits-Verilog-Solutions
Users that are interested in HDLBits-Verilog-Solutions are comparing it to the libraries listed below
Sorting:
- My solution to the problem set on HDLBits.☆26Updated 5 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆438Updated 5 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆165Updated last year
- 100 Days of RTL☆403Updated last year
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆280Updated 6 months ago
- Verilog HDL files☆161Updated last year
- 30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills a…☆52Updated 2 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆147Updated 5 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆122Updated 3 years ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆30Updated 4 months ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆31Updated last year
- opensource EDA tool flor VLSI design☆35Updated 2 years ago
- Design of a 16-Bit CPU using Verilog☆43Updated 6 years ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆367Updated 2 years ago
- SystemVerilog Tutorial☆185Updated 2 weeks ago
- ECE 3300 HDL Code☆61Updated 2 years ago
- This repo provide an index of VLSI content creators and their materials☆162Updated last year
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆22Updated 4 months ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆32Updated 5 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆66Updated 2 years ago
- ☆117Updated last year
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆52Updated last year
- A Single Cycle Risc-V 32 bit CPU☆55Updated last week
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆19Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆81Updated 2 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆158Updated 4 years ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆143Updated 2 months ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆128Updated 2 months ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆26Updated 11 months ago