Alternatives and similar repositories for HDLBits-Verilog-Solutions

Users that are interested in HDLBits-Verilog-Solutions are comparing it to the libraries listed below

• y-C-x / HDLBits_Solution
  My solution to the problem set on HDLBits.
  ☆26Updated 5 years ago
• Test134n / 32-Verilog-Mini-Projects
  Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …
  ☆22Updated 3 months ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆402Updated last year
• abdelazeem201 / ASIC-Design-Roadmap
  The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…
  ☆422Updated 4 months ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆275Updated 5 months ago
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆366Updated 2 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆165Updated last year
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆143Updated 5 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆468Updated 3 weeks ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆320Updated 7 years ago
• EkthaReddy / RISC-V-Single-Cycle-Processor
  In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…
  ☆19Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆529Updated 4 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆696Updated 2 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆482Updated 5 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆392Updated 2 months ago
• Akashtailor-exe / 30-days-of-verilog
  30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills a…
  ☆50Updated 2 years ago
• mikinty / Hardware-Engineer-Interview-Questions
  For aspiring hardware engineers out there.
  ☆78Updated 8 months ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆14Updated 2 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆333Updated 3 years ago
• maazm007 / vsdsquadron-mini-internship
  VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
  ☆30Updated 4 months ago
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆23Updated 3 years ago
• martinKindall / risc-v-single-cycle
  A Single Cycle Risc-V 32 bit CPU
  ☆54Updated last month
• UndefeatedSunny / VLSI-Interview-Questions
  Digital Design verilog tricky problems having industry standards
  ☆26Updated 5 years ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆160Updated last year
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆581Updated 3 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆438Updated 3 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,132Updated 4 years ago
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆29Updated last year
• Ummidichandrika / 100-Days-of-RTL
  ☆117Updated last year
• Subhasis-Sahu / SFAL-VSD
  ☆13Updated last year