Adrofier / HDLBits-Verilog-SolutionsLinks
Solutions to HDLBits Verilog Problem Set
☆39Updated 6 months ago
Alternatives and similar repositories for HDLBits-Verilog-Solutions
Users that are interested in HDLBits-Verilog-Solutions are comparing it to the libraries listed below
Sorting:
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆290Updated 8 months ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆454Updated 6 months ago
- My solution to the problem set on HDLBits.☆26Updated 5 years ago
- 100 Days of RTL☆406Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆175Updated 2 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆159Updated 5 years ago
- It contains a curated list of awesome RISC-V Resources.☆294Updated last year
- A verilog based 5-stage pipelined RISC-V Processor code.☆33Updated 5 years ago
- A Single Cycle Risc-V 32 bit CPU☆65Updated 2 weeks ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆371Updated 2 years ago
- opensource EDA tool flor VLSI design☆36Updated 2 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆124Updated 3 years ago
- 30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills a…☆55Updated 2 years ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆31Updated 6 months ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆33Updated last year
- This repo provide an index of VLSI content creators and their materials☆164Updated last year
- Design of a 16-Bit CPU using Verilog☆45Updated 6 years ago
- ☆116Updated 2 years ago
- Verilog HDL files☆170Updated last year
- Implementation of RISC-V RV32I☆28Updated 3 years ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆153Updated 3 months ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆59Updated last year
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆32Updated last year
- lowRISC Style Guides☆476Updated 2 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆555Updated 4 years ago
- A collection of great digital IC project/tutorial/website etc..☆143Updated 3 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆168Updated 4 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆73Updated 2 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- A roadmap for those who want to build a career as an FPGA / ASIC Engineer☆495Updated last year