Noris4est / I2C-FPGA-Verilog-HDL
In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardware description language.
☆12Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for I2C-FPGA-Verilog-HDL
- UART design in SV and verification using UVM and SV☆38Updated 4 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- Hardware implementation of HDR image producing algorithm☆15Updated 2 years ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆34Updated 4 years ago
- UVM resource from github, run simulation use YASAsim flow☆26Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆55Updated 9 months ago
- A python project to automatically generate the UVM testbench document.☆19Updated 8 months ago
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆89Updated 6 years ago
- FFT implement by verilog_测试验证已通过☆52Updated 8 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆20Updated 2 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆26Updated 3 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- ☆34Updated 9 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆40Updated 3 years ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆14Updated 4 years ago
- ☆53Updated 8 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆44Updated last year
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆111Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- 基于FPGA的图像处理模块(出自 于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆46Updated 4 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆49Updated 2 years ago
- Implementation of the PCIe physical layer☆30Updated last week
- FPGA和USB3.0桥片实现USB3.0通信☆54Updated 2 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆12Updated 2 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆37Updated 11 months ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆29Updated 3 years ago