Noris4est / I2C-FPGA-Verilog-HDL
In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardware description language.
☆14Updated 4 years ago
Alternatives and similar repositories for I2C-FPGA-Verilog-HDL:
Users that are interested in I2C-FPGA-Verilog-HDL are comparing it to the libraries listed below
- UART design in SV and verification using UVM and SV☆40Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 9 months ago
- System on Chip verified with UVM/OSVVM/FV☆23Updated last month
- UVM resource from github, run simulation use YASAsim flow☆27Updated 4 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆20Updated 5 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆20Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆31Updated 3 years ago
- DDR3 function verification environment in UVM☆23Updated 6 years ago
- SPI interface connect to APB BUS with Verilog HDL☆27Updated 3 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆15Updated last year
- Verification IP for APB protocol☆57Updated 4 years ago
- ☆24Updated 3 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- APB to I2C☆39Updated 10 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆41Updated 4 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆43Updated 11 months ago
- PCIE 5.0 Graduation project (Verification Team)☆61Updated last year
- ☆35Updated 9 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆27Updated 6 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- AXI Interconnect☆47Updated 3 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 6 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆29Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆48Updated 4 years ago