Noris4est / I2C-FPGA-Verilog-HDLLinks
In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardware description language.
☆17Updated 5 years ago
Alternatives and similar repositories for I2C-FPGA-Verilog-HDL
Users that are interested in I2C-FPGA-Verilog-HDL are comparing it to the libraries listed below
Sorting:
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆76Updated last year
- SPI interface connect to APB BUS with Verilog HDL☆31Updated 3 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- Verification IP for APB protocol☆66Updated 4 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆61Updated 2 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆101Updated 7 years ago
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆29Updated last year
- AXI Interconnect☆49Updated 3 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 3 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆56Updated last year
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 4 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆55Updated 3 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆48Updated 4 years ago
- APB to I2C☆41Updated 10 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- Bitmap Processing Library & AXI-Stream Video Image VIP☆32Updated 3 years ago
- ☆13Updated 3 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- ☆20Updated 2 years ago
- This is the repository for the IEEE version of the book☆66Updated 4 years ago
- ☆36Updated 9 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆52Updated 4 years ago