Shahriar-0 / Digital-Logic-Design-Lab-Experiments-S2023Links
Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators
☆11Updated 2 years ago
Alternatives and similar repositories for Digital-Logic-Design-Lab-Experiments-S2023
Users that are interested in Digital-Logic-Design-Lab-Experiments-S2023 are comparing it to the libraries listed below
Sorting:
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆12Updated 2 years ago
- Sobel is first order or gradient based edge operator for images and it is implemented using verilog.☆14Updated 5 years ago
- Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional N…☆19Updated last year
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆14Updated 6 years ago
- Digital IC design and vlsi notes☆12Updated 5 years ago
- 关于数字IC的笔试面试题☆13Updated 6 years ago
- 使用Cordic算法函数运算，在资源受限的设备上运行（如资源较少的FPGA、嵌入式MCU），避免了浮点运算、乘法、除法，只用移位和加法函数的计算。☆11Updated last year
- 使用FPGA制作机器人，并使用python建立上位机，FPGA机器人通过控制ESP8266通过WiFi进行无线通讯，来达到上位机控制FPGA机器人的目的☆26Updated 5 years ago
- 基于FPGA-Pynq的车牌识别系统。The LPR system of FPGA-Pynq☆13Updated 6 years ago
- Physical Downlink Shared Channel (PDSCH) in 5G New Radio.☆12Updated last year
- wifi☆12Updated 8 years ago
- Controller module for RISC-V core CI/CD☆17Updated 7 months ago
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆11Updated last year
- Hardware implementation of HDR image producing algorithm☆15Updated 3 years ago
- 基于GSConv+SlimNeck的YOLOv5的消防通道占用检测系统☆10Updated 2 years ago
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆27Updated 7 years ago
- HW and SW based implementation of Canny Edge Detection Algorithm.☆12Updated 7 years ago
- 本文提出了一种基于多视图卷积神经网络的三维物体识别算法，以实现三维物体的准确识别。首先实现一个标准的卷积神经网络架构，该架构经过训练可以独立地识别形状的渲染视图，以实现即使从单一视图中也可以识别出一个三维形状。随后使用该三维物体多个角度的二维视图通过卷积神经网络识别的结果进…☆11Updated 3 years ago
- DSP University Project - Matlab, Simulations, and Verilog Files☆13Updated 5 years ago
- lusixing / Joint-Decoding-Framework-for-LDPC-coded-MIMO-SCMA-Systems-Based-on-Expectation-PropagationA generalized efficient decoding framework that performs joint decoding for non-binary low density parity check code (NB-LDPC) coded spa…☆13Updated 8 months ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Updated 13 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Verilog code for a low power RFID chip that will communicate with I2C sensors.☆13Updated 11 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Updated 7 years ago
- Docker image with Xilinx FPGA Tools (Vivado - SDAccel) usable with GUI on Mac☆10Updated 7 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆20Updated 5 years ago
- Learning Environment-aware and hardware-compatible beam-forming codebooks☆15Updated 5 years ago
- 2020 xilinx summer school☆19Updated 5 years ago
- ☆10Updated last year
- FIR implemention with Verilog☆50Updated 6 years ago