Alternatives and similar repositories for The-car-base-on-FPGA

Users that are interested in The-car-base-on-FPGA are comparing it to the libraries listed below

• tianxiaogua / FPGA-Robot
  使用FPGA制作机器人，并使用python建立上位机，FPGA机器人通过控制ESP8266通过WiFi进行无线通讯，来达到上位机控制FPGA机器人的目的
  ☆22Updated 4 years ago
• markos-stefanidis / FPGA-Based-HDR-algorithm
  Hardware implementation of HDR image producing algorithm
  ☆16Updated 2 years ago
• jchengX / MAC_BFM
  wifi
  ☆11Updated 8 years ago
• ahegazy / vlsi-notes
  Digital IC design and vlsi notes
  ☆12Updated 5 years ago
• yuezhao1 / ANLU_fpga
  使用国产FPGA厂商安路公司的开发板做的一款基于FPGA的智能导盲杖系统。利用百度LBS开放平台做到自主导航，与Arduino互联实现PID算法，摄像头识别红绿灯，超声波自主避障，语音识别，一键拨打紧急联系人等等
  ☆24Updated 5 years ago
• programer-guan / digital_ic_verification
  数字IC验证案例（SV and UVM）
  ☆26Updated 4 years ago
• gauravtewari / python-to-verilog
  Generate a Verilog Source file and testbench file for a given Moore FSM
  ☆17Updated 12 years ago
• zengchenglong / interview_digital_IC
  关于数字IC的笔试面试题
  ☆9Updated 5 years ago
• Noris4est / I2C-FPGA-Verilog-HDL
  In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…
  ☆18Updated 5 years ago
• Grootzz / Verilog-FIR
  FIR implemention with Verilog
  ☆48Updated 6 years ago
• deepaktabraham / FPGA-Acceleration-of-Canny-Edge-Detection-Algorithm
  HW and SW based implementation of Canny Edge Detection Algorithm.
  ☆12Updated 7 years ago
• JasonCarter92 / 16QAM-Transmitter-Reciever
  DSP University Project - Matlab, Simulations, and Verilog Files
  ☆11Updated 5 years ago
• codyps / wimax_ofdm
  Partial Verilog implimentation of a WiMAX OFDM Phy
  ☆19Updated 13 years ago
• txzing / modbus_crc_verilog
  FPGA纯逻辑实现modbus通信
  ☆20Updated 2 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆16Updated 5 years ago
• xkw168 / Digital-recognition
  digital recognition base on FPGA
  ☆13Updated 5 years ago
• muneeb-mbytes / uvm_tb_arch_doc_py
  A python project to automatically generate the UVM testbench document.
  ☆20Updated last year
• tharunchitipolu / sobel-edge-detector
  Sobel is first order or gradient based edge operator for images and it is implemented using verilog.
  ☆14Updated 4 years ago
• DexWen / LMS-Adaptive-filter
  LMS-Adaptive Filter implement using verilog and Matlab
  ☆44Updated 8 years ago
• JacoboJin / RISCV-on-PYNQ-Z2
  This repo is to inplemente the riscv soc on the xilinx pynq-z2 board
  ☆11Updated last year
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 5 years ago
• funningboy / vim
  UVM/systemverilog/verilog/python VIM IDE
  ☆16Updated 11 years ago
• Starrynightzyq / ZYNQ-PYNQ-Z2-Gobang
  2018第二届全国大学生FPGA创新设计邀请赛的作品
  ☆60Updated 6 years ago
• CospanDesign / verilog_ppfifo_demo
  Simple demo showing how to use the ping pong FIFO
  ☆14Updated 9 years ago
• Elrori / OV_camera_on_FPGA
  OV7670 (Verilog HDL)Drive for FPGA
  ☆17Updated 6 years ago
• ajackevic / ELEC5882
  The Design and Implementation of a Pulse Compression Filter on an FPGA.
  ☆30Updated 3 years ago
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆19Updated 6 years ago
• chenjianqu / Pynq-LicensePlateRecognition
  基于FPGA-Pynq的车牌识别系统。The LPR system of FPGA-Pynq
  ☆11Updated 6 years ago
• qxdn / 16QAM
  16QAM modulation and demodulation by Verilog
  ☆20Updated 4 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago