Alternatives and similar repositories for de10-nano:

Users that are interested in de10-nano are comparing it to the libraries listed below

• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆634Updated 2 months ago
• projf / display_controller
  FPGA display controller with support for VGA, DVI, and HDMI.
  ☆225Updated 5 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆296Updated last year
• xesscorp / VHDL_Lib
  Library of VHDL components that are useful in larger designs.
  ☆232Updated last year
• ultraembedded / FPGAmp
  720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
  ☆275Updated 4 years ago
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆382Updated this week
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆300Updated last week
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆257Updated 2 months ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆229Updated 2 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆427Updated 3 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆529Updated last month
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆420Updated 6 months ago
• damdoy / ice40_ultraplus_examples
  Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
  ☆260Updated last year
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆183Updated last year
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆244Updated 6 years ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆236Updated 2 weeks ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆401Updated 2 months ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆444Updated 2 years ago
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆642Updated this week
• YosysHQ / apicula
  Project Apicula 🐝: bitstream documentation for Gowin FPGAs
  ☆544Updated this week
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆391Updated last week
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆327Updated last week
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆565Updated this week
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆159Updated this week
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆269Updated 7 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆606Updated last week
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆117Updated 4 years ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆622Updated last week
• nandland / nandland
  All code found on nandland is here. underconstruction.gif
  ☆325Updated 2 years ago
• TimRudy / ice-chips-verilog
  IceChips is a library of all common discrete logic devices in Verilog
  ☆140Updated 4 months ago