martinKindall / mips_cpu
Single Cycle 32 bit MIPS
☆18Updated 2 years ago
Alternatives and similar repositories for mips_cpu:
Users that are interested in mips_cpu are comparing it to the libraries listed below
- Playing around with Formal Verification of Verilog and VHDL☆54Updated 3 years ago
- Pipelined RISC-V RV32I Core in Verilog☆37Updated last year
- ☆84Updated last year
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆117Updated 4 years ago
- Learning to do things with the Skywater 130nm process☆75Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆57Updated 2 months ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆51Updated 4 months ago
- An open-source HDL register code generator fast enough to run in real time.☆40Updated this week
- ☆127Updated last month
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆85Updated 4 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆141Updated this week
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆65Updated 2 years ago
- OSVVM Documentation☆32Updated last month
- A getting started presentation (with examples) about how to use FLOSS for FPGA development.☆35Updated last year
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆119Updated 3 years ago
- Verilog HDL files☆118Updated 8 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆51Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆77Updated last year
- Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application☆41Updated 7 months ago
- FPGA Logic Analyzer and GUI☆114Updated 2 years ago
- Control and Status Register map generator for HDL projects☆109Updated this week
- Verilog implementation of a RISC-V core☆108Updated 6 years ago
- SystemVerilog Tutorial☆121Updated this week
- Absolute beginner's guide to the de10-nano☆206Updated 10 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆43Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 2 months ago
- Slides and lab instructions for the mastering MicroBlaze session☆34Updated 2 years ago
- Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.☆31Updated 2 years ago