martinKindall / mips_cpu
Single Cycle 32 bit MIPS
☆20Updated 2 years ago
Alternatives and similar repositories for mips_cpu
Users that are interested in mips_cpu are comparing it to the libraries listed below
Sorting:
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆164Updated last week
- Playing around with Formal Verification of Verilog and VHDL☆57Updated 4 years ago
- Pipelined RISC-V RV32I Core in Verilog☆38Updated 2 years ago
- A getting started presentation (with examples) about how to use FLOSS for FPGA development.☆35Updated last year
- This repo provide an index of VLSI content creators and their materials☆149Updated 8 months ago
- An open-source HDL register code generator fast enough to run in real time.☆64Updated 2 weeks ago
- ☆93Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆57Updated 2 years ago
- Learning to do things with the Skywater 130nm process☆78Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆91Updated 3 weeks ago
- Control and Status Register map generator for HDL projects☆116Updated this week
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆128Updated 3 years ago
- FPGA Logic Analyzer and GUI☆130Updated 2 years ago
- SystemVerilog Tutorial☆142Updated this week
- A set of Wishbone Controlled SPI Flash Controllers☆80Updated 2 years ago
- OSVVM Documentation☆33Updated last week
- Flexible VHDL library☆184Updated last year
- Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.☆33Updated 3 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 3 months ago
- Slides and lab instructions for the mastering MicroBlaze session☆35Updated 2 years ago
- ☆155Updated 2 years ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆95Updated 9 years ago
- ☆132Updated 5 months ago
- SPI Master and Slave components to be used in all of FPGAs, written in VHDL.☆37Updated 5 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆83Updated this week
- Home of the open-source EDA course.☆38Updated 2 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆46Updated last year
- Verilog digital signal processing components☆135Updated 2 years ago
- HDLRegression: Simple, efficient, Python3-based FPGA regression test runner. Streamline the verification workflow.☆24Updated last month
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆31Updated 2 years ago