martinKindall / mips_cpu
Single Cycle 32 bit MIPS
☆17Updated last year
Related projects ⓘ
Alternatives and complementary repositories for mips_cpu
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆90Updated 3 years ago
- Pipelined RISC-V RV32I Core in Verilog☆36Updated last year
- RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.☆18Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆116Updated 4 years ago
- FPGA Logic Analyzer and GUI☆90Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆108Updated this week
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆68Updated 11 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆62Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆36Updated this week
- Verilog modules required to get the OV7670 camera working☆63Updated 6 years ago
- Verilog HDL files☆100Updated 5 months ago
- SystemVerilog Tutorial☆114Updated 11 months ago
- Wishbone interconnect utilities☆37Updated 5 months ago
- Slides and lab instructions for the mastering MicroBlaze session☆33Updated 2 years ago
- ☆121Updated last year
- Simple UART controller for FPGA written in VHDL☆91Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆76Updated 4 years ago
- OSVVM Documentation☆30Updated last month
- Verilog implementation of multi-stage 32-bit RISC-V processor☆74Updated 4 years ago
- A Single Cycle Risc-V 32 bit CPU☆34Updated last year
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆210Updated last week
- Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application☆30Updated 5 months ago
- ☆120Updated 2 years ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆26Updated 2 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆29Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆66Updated this week
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆53Updated 3 years ago
- Opensource DDR3 Controller☆216Updated this week