jiegec / HT42B534USB2UARTLinks
A simple USB to UART board designed with KiCad.
☆14Updated 2 years ago
Alternatives and similar repositories for HT42B534USB2UART
Users that are interested in HT42B534USB2UART are comparing it to the libraries listed below
Sorting:
- A naive verilog/systemverilog formatter☆21Updated 7 months ago
- A hand-written recursive decent Verilog parser.☆10Updated 3 years ago
- What if everything is a io_uring?☆16Updated 3 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆14Updated 3 years ago
- PoC LoongArch - RISC-V emulator☆32Updated last year
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆41Updated 2 months ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆30Updated 5 years ago
- Paging Debug tool for GDB using python☆13Updated 3 years ago
- A router IP written in Verilog.☆12Updated 5 years ago
- Tsinghua Advanced Networking Labs on FPGA☆38Updated last year
- ☆22Updated 3 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- RV32I by cats☆15Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- Warning: 🕳 ahead!☆16Updated 5 years ago
- My knowledge base☆72Updated last week
- A Symmetric Multiprocessing OS Kernel over RISC-V☆32Updated 3 years ago
- 在RISC-V处理器上实现一个轻量级的Hypervisor。☆12Updated 4 years ago
- [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)☆14Updated 5 years ago
- Test run any program on D1 Nezha board flash