jiegec / HT42B534USB2UARTLinks
A simple USB to UART board designed with KiCad.
☆15Updated 2 years ago
Alternatives and similar repositories for HT42B534USB2UART
Users that are interested in HT42B534USB2UART are comparing it to the libraries listed below
Sorting:
- A naive verilog/systemverilog formatter☆21Updated 5 months ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- A hand-written recursive decent Verilog parser.☆11Updated 2 years ago
- What if everything is a io_uring?☆16Updated 2 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆31Updated 5 years ago
- HERMES: sHallow dirEctory stRucture Many-filE fileSystem☆20Updated 6 years ago
- Compile Time RapidJSON: A compile time C++ header only JSON library without bloating yet another hand-crafted JSON parser based on RapidJ…☆15Updated 5 years ago
- PoC LoongArch - RISC-V emulator☆32Updated last year
- ☆23Updated 3 years ago
- Project template for Artix-7 based Thinpad board☆48Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆63Updated 3 years ago
- CIDR union / subtraction☆14Updated this week
- Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University☆11Updated 6 years ago
- Warning: 🕳 ahead!☆16Updated 5 years ago
- A router IP written in Verilog.☆13Updated 5 years ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆32Updated 3 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- RV32I by cats☆16Updated last year
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆41Updated last week
- My knowledge base☆63Updated last week
- A hardware accelerated IP packet forwarder running on programmable ICs☆16Updated 2 years ago
- Tsinghua Advanced Networking Labs on FPGA☆38Updated 9 months ago
- Paging Debug tool for GDB using python☆13Updated 3 years ago
- 网络学堂 PC 端 App☆21Updated 2 years ago
- 自嗨虚拟化软件 - 'Enjoy yourself' type-1 hypervisor software☆25Updated 3 years ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT☆25Updated 2 months ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 3 years ago
- 在RISC-V处理器上实现一个轻量级的Hypervisor。☆12Updated 4 years ago