Benchmarking a single‑prompt Rust OS kernel implementation, comparing Claude Code Fable, Opus, and Sonnet.
☆43Jul 10, 2026Updated this week
Alternatives and similar repositories for JiegeOSBench
Users that are interested in JiegeOSBench are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A hand-written recursive decent Verilog parser.☆10Jun 28, 2026Updated 2 weeks ago
- CPU micro benchmarks☆84Jun 19, 2026Updated 3 weeks ago
- Plagiarism detection tool in Rust (inspired by Stanford Moss)☆54Jun 28, 2026Updated 2 weeks ago
- Compiling finite generators to digital logic. WIP☆13Aug 24, 2020Updated 5 years ago
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆30May 14, 2020Updated 6 years ago
- MCP server to read waveform files☆43May 4, 2026Updated 2 months ago
- RV32I by cats☆15Sep 4, 2023Updated 2 years ago
- 网络学堂 PC 端 App☆21Jun 21, 2026Updated 3 weeks ago
- A router IP written in Verilog.☆12Dec 20, 2019Updated 6 years ago
- A naive verilog/systemverilog formatter☆22Apr 2, 2026Updated 3 months ago
- The cold linker☆73May 7, 2026Updated 2 months ago
- Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT☆38Jun 18, 2025Updated last year
- PKU CompNet'19 Lab 2 - Homebrew TCP☆12Nov 29, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Backend & Frontend for JieLabs☆22Mar 3, 2023Updated 3 years ago
- ☆20Dec 11, 2024Updated last year
- Warning: 🕳 ahead!☆16Jan 8, 2020Updated 6 years ago
- Convert regex(es) to dfa.☆14Apr 30, 2021Updated 5 years ago
- A 3d printed case design for Lichee Pi 4A☆11May 13, 2023Updated 3 years ago
- Booting multi-processors on x86 bare-metal.☆12Feb 25, 2022Updated 4 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Jan 21, 2023Updated 3 years ago
- Project template for Artix-7 based Thinpad board☆52Sep 13, 2025Updated 10 months ago
- HERMES: sHallow dirEctory stRucture Many-filE fileSystem☆20Jun 9, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Documentation for Router Lab☆74May 20, 2026Updated last month
- A database management system implemented in Rust from scratch.☆21Jul 24, 2021Updated 4 years ago
- Relaxed Rust (for cats)☆14Nov 20, 2019Updated 6 years ago
- Loongarch Emulator☆19Mar 14, 2025Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Feb 17, 2022Updated 4 years ago
- A headless MCP server for IDA Pro. It lets AI agents open and analyze multiple IDA databases on demand, without launching the IDA manully…☆18Feb 28, 2026Updated 4 months ago
- An AlphaZero engine for Saiblo Connect4, featuring a pure Python implementation of key KataGo techniques.☆18Apr 21, 2026Updated 2 months ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆94Aug 29, 2023Updated 2 years ago
- THU Computational Graphics course projects.☆38May 12, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Convert shared libraries into relocatable objects☆10Dec 23, 2023Updated 2 years ago
- Compile Optimization Guided Binary Translator (using llvm as infrastructure)☆53Aug 12, 2024Updated last year
- Follow nginx log, and find out bad guys!☆24May 10, 2026Updated 2 months ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- An advanced cross-platform serial port utility☆28Dec 28, 2025Updated 6 months ago
- Vijos: Vijos Isn't Just an Operating System☆10May 31, 2020Updated 6 years ago