Alternatives and similar repositories for UCAS-CALab-mycpu_verify

Users that are interested in UCAS-CALab-mycpu_verify are comparing it to the libraries listed below

• cebarobot / UCAS-Computer-Architecture-Lab
  计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集
  ☆18Updated 3 years ago
• spokeyjoe / LoongArchCPU
  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.
  ☆23Updated last year
• EricJin2002 / UCAS-CA-2022
  一个单发射五级静态流水CPU，采用龙芯32位精简版指令集，支持异常和中断处理，使用AXI总线接口，已集成TLB模块
  ☆15Updated 2 years ago
• Corle-hyz / UCAS-COD-Lab
  中国科学院大学(UCAS)2020年春季学期计算机组成原理实验课作业
  ☆18Updated 3 years ago
• cquwei-cx / cpu20220108
  MIPS 57条指令五级流水线cpu (verilog实现+详细注释)
  ☆11Updated 3 years ago
• RegiaYoung / RISC-V-CPU
  记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU
  ☆13Updated 3 years ago
• cebarobot / UCAS-CALab-mycpu_axi_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15
  ☆13Updated 4 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆136Updated 11 months ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆81Updated 5 years ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆35Updated 4 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆36Updated 11 months ago
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆28Updated 5 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆28Updated 2 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆66Updated 2 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆43Updated 4 years ago
• SinnLiu / CPU_Design_MIPS
  《CPU设计实战》学习记录及代码
  ☆12Updated last year
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆45Updated 2 years ago
• yyNoBug / RISCV-CPU
  A FPGA-supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL. Achieve good performance due to optimizations like branch p…
  ☆9Updated 5 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆128Updated 4 years ago
• yang-le / riscv_cpu
  a simple riscv cpu
  ☆23Updated 2 years ago
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆11Updated 3 months ago
• Rzfly / simple_riscv_soft_core
  This is a simple Risc-v core for software simulation on FPGA.
  ☆8Updated 3 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• Sevenqi7 / NSCSCC-2022
  2022龙芯杯个人赛三等奖作品
  ☆14Updated last year
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆54Updated last year
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆51Updated 3 years ago
• sailordiary / computer-systems-ucas
  中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
  ☆32Updated 7 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 9 months ago