ym31433 / NPU-Architecture
CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
☆18Updated 7 years ago
Related projects: ⓘ
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆29Updated last year
- ☆24Updated 5 years ago
- ☆23Updated 4 years ago
- verification of simple axi-based cache☆16Updated 5 years ago
- DMA controller for CNN accelerator☆12Updated 7 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆27Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆39Updated 3 years ago
- ☆14Updated last year
- ☆31Updated 2 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- Design and UVM-TB of RISC -V Microprocessor☆12Updated 2 months ago
- eyeriss-chisel3☆35Updated 2 years ago
- ☆17Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆32Updated 2 years ago
- SoC Based on ARM Cortex-M3☆24Updated 4 months ago
- General Purpose AXI Direct Memory Access☆44Updated 4 months ago
- YSYX RISC-V Project NJU Study Group☆12Updated 2 years ago
- tpu-systolic-array-weight-stationary☆17Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆21Updated 5 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆27Updated 3 years ago
- ☆16Updated 5 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆24Updated last year
- ☆35Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆10Updated 3 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆34Updated 7 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆20Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆43Updated 3 months ago
- Clock Domain Crossing Design(use MCP formulation without feedback)基于MCP不带反馈的跨时钟域设计☆10Updated 4 years ago