williamqwu / VE370-Pipelined-Processor

Related projects ⓘ

Alternatives and complementary repositories for VE370-Pipelined-Processor

• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆31Updated 6 years ago
• z4yx / vivado-docker
  Dockerfile with Vivado for CI
  ☆28Updated 4 years ago
• MaxXSoft / Bossa
  BOOM's Simulation Accelerator.
  ☆11Updated 2 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆33Updated 3 years ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆16Updated this week
• thu-cs-lab / Digital-Design-Docs
  Documentation for Digital Design course
  ☆19Updated 3 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆34Updated 10 months ago
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆11Updated this week
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆45Updated 11 months ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated last year
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆54Updated 2 years ago
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆11Updated last year
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• jiegec / kb
  My knowledge base
  ☆38Updated last week
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated last year
• yamak / axi-nodes
  ☆19Updated 2 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆35Updated 2 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆24Updated this week
• chipsalliance / playground
  chipyard in mill :P
  ☆75Updated 11 months ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆26Updated 4 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆27Updated 10 months ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆31Updated last year
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated 7 months ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆10Updated 7 months ago
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆83Updated 11 months ago
• miaochenlu / Gem5_tutorials
  ☆16Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆21Updated 8 months ago