ZJUArch / verilog-general-guideLinks
☆18Updated 7 years ago
Alternatives and similar repositories for verilog-general-guide
Users that are interested in verilog-general-guide are comparing it to the libraries listed below
Sorting:
- GNC is Not C. It is intended for a better and more effective c language.☆18Updated 3 years ago
- Introduction to Computer Systems (II), Spring 2021☆51Updated 3 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆48Updated last year
- Recommended coding standard of Verilog and SystemVerilog.☆34Updated 3 years ago
- 龙芯杯21个人赛作品☆36Updated 3 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆36Updated 3 years ago
- 计算机组成原理课程32位监控程序☆48Updated 5 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Updated 7 years ago
- RISC-V SingleCycle/Pipeline CPU (lab of ZJU Computer System Series)☆15Updated last year
- Java implementation of MIPS instruction set and graphical emulator. Designed for ZJU SWORD-II.☆34Updated 4 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- CQU Dual Issue Machine☆36Updated 11 months ago
- nscscc2018☆26Updated 6 years ago
- ☆20Updated last week
- Implementing the Precise Runahead (HPCA'20) in gem5☆11Updated last year
- My project for the course "Logic and Computer Design Fundamentals"(LCDF) in Zhejiang University☆12Updated 8 years ago
- Microarchitecture diagrams of several CPUs☆36Updated last month
- ☆17Updated 3 years ago
- The MiniDecaf test cases.☆17Updated 3 weeks ago
- Project template for Artix-7 based Thinpad board☆46Updated 2 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆80Updated last year
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 7 months ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated last year
- ☆34Updated 5 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆42Updated 10 months ago
- Documentation for Digital Design course☆20Updated 3 months ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- gem5 相关中文笔记☆14Updated 3 years ago
- Being a full-stack hacker, RISCV, LLVM, and more.☆17Updated 3 years ago