☆18Dec 2, 2017Updated 8 years ago
Alternatives and similar repositories for verilog-general-guide
Users that are interested in verilog-general-guide are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- All the verilog code I wrote in hardware Course☆10Sep 22, 2019Updated 6 years ago
- QSC Tech Recruitment 2020 Autumn Round Two☆10Oct 4, 2020Updated 5 years ago
- Summaries for some courses in ZJU☆63Jun 30, 2020Updated 5 years ago
- ☆16Mar 18, 2025Updated last year
- gem5 相关中文笔记☆17Dec 2, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- C-like language compiler, the final project of ZJU Compiler Principle course☆43Oct 9, 2022Updated 3 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- 用于研读LevelDB源码时进行注释，持续更新☆12Feb 23, 2023Updated 3 years ago
- 记录了在三本软工两年来的课程资料， 进击吧少年☆10Dec 10, 2022Updated 3 years ago
- ☆22Nov 3, 2025Updated 5 months ago
- A Ray-based LLM server compatible with OpenAI API☆12Mar 12, 2024Updated 2 years ago
- The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.☆45Apr 11, 2021Updated 5 years ago
- A VSCode theme designed for macOS Dark Mode☆10Apr 1, 2022Updated 4 years ago
- 基于 jieba-rs 的中文分词插件☆12Nov 1, 2025Updated 5 months ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- FPGA-based ball-maze game, Digital Logic Design course project.☆11Sep 25, 2018Updated 7 years ago
- Chisel Learning Journey☆109Apr 5, 2023Updated 3 years ago
- Scratchpad about Linux, Compiler and Virtualization☆82Feb 18, 2026Updated 2 months ago
- 数字逻辑课程资料☆12Dec 28, 2017Updated 8 years ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- A fish shell plugin that allows you to refresh the prompt BEFORE the next command is executed to display updated time, git state, etc. at…☆27Jan 5, 2025Updated last year
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆10Apr 29, 2024Updated last year
- ☆10Oct 8, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆33Feb 6, 2020Updated 6 years ago
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆13Aug 9, 2019Updated 6 years ago
- ☆15Updated this week
- DirectX linux drivers for GPU-PV (dkms)☆15Aug 27, 2023Updated 2 years ago
- openrussian-cli has permanently moved to https://git.fmsbw.de/openrussian-cli/☆13Oct 5, 2025Updated 6 months ago
- ☆14Sep 8, 2019Updated 6 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 6 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- LLM-DSE: Searching Accelerator Parameters with LLM Agents☆13May 22, 2025Updated 10 months ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated 2 months ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆15Mar 24, 2023Updated 3 years ago
- ☆10Dec 28, 2020Updated 5 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- A Mill plugin that generates and SCIP index for your build.☆11Aug 26, 2025Updated 7 months ago