Alternatives and similar repositories for verilog-general-guide

Users that are interested in verilog-general-guide are comparing it to the libraries listed below

• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 3 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆52Updated 4 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆82Updated 2 years ago
• jiegec / kb
  My knowledge base
  ☆72Updated 3 weeks ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆50Updated 2 months ago
• MaxXSoft / Bossa
  BOOM's Simulation Accelerator.
  ☆13Updated 3 years ago
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆13Updated 2 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆108Updated 6 years ago
• YAVGroup / Verilog-OJ
  Online judge server for Verilog | verilogoj.ustc.edu.cn
  ☆82Updated last year
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆36Updated 4 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆42Updated 7 years ago
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆52Updated 2 months ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆119Updated last year
• thu-cs-lab / supervisor-rv
  计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位
  ☆125Updated 2 months ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆44Updated 5 years ago
• SamAinsworth / gem5-triangel
  ☆21Updated 8 months ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 7 years ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆18Updated 3 years ago
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆50Updated 5 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆117Updated 5 years ago
• iFuProcessor / iFuCore
  ☆20Updated last year
• jiegec / blog-source
  The source of my blog.
  ☆54Updated last week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated this week
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆66Updated last month