Alternatives and similar repositories for verilog-general-guide:

Users that are interested in verilog-general-guide are comparing it to the libraries listed below

• jiegec / blog-source
  The source of my blog.
  ☆22Updated this week
• Keytoyze / Sword_emulator
  Java implementation of MIPS instruction set and graphical emulator. Designed for ZJU SWORD-II.
  ☆34Updated 4 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆34Updated 3 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆47Updated last year
• tsreaper / verilog-gobang-game-with-ai
  My project for the course "Logic and Computer Design Fundamentals"(LCDF) in Zhejiang University
  ☆12Updated 7 years ago
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆50Updated 3 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆39Updated 7 years ago
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆48Updated 4 years ago
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆46Updated last year
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆106Updated 5 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆43Updated 4 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆34Updated 3 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• thu-cs-lab / supervisor-rv
  计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位
  ☆117Updated 7 months ago
• decaf-lang / minidecaf-tests
  The MiniDecaf test cases.
  ☆17Updated last year
• iBug / USTC-RV-Chisel
  Chisel implementation of USTC RISC-V
  ☆8Updated 4 years ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆39Updated last year
• TonyCrane / CraneCPU
  RISC-V SingleCycle/Pipeline CPU (lab of ZJU Computer System Series)
  ☆15Updated last year
• ziyue-pan / GNC
  GNC is Not C. It is intended for a better and more effective c language.
  ☆18Updated 3 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆35Updated 10 months ago
• HITSZ-CDP / cdp-tests
  《计算机设计与实践》测试框架
  ☆15Updated 2 years ago
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆11Updated last year
• SamAinsworth / gem5-triangel
  ☆13Updated last month
• aniketp / ipcp-dsp
  Instruction Pointer Classifier and Dynamic Degree Stream based Hardware Cache Prefetching
  ☆16Updated 5 years ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆78Updated last year
• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆38Updated 5 years ago
• mytbk / gem5-docs
  gem5 相关中文笔记
  ☆14Updated 3 years ago
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆35Updated 3 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago