Alternatives and similar repositories for Verilog-OJ:

Users that are interested in Verilog-OJ are comparing it to the libraries listed below

• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆34Updated 3 years ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆74Updated last year
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆111Updated 3 months ago
• nscscc2019ucas / nscscc2019ucas
  ☆33Updated 5 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆41Updated 4 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆34Updated 3 years ago
• yuxguo / USTC-ComputerArchitecture-2020S
  Code for "Computer Architecture" in 2020 Spring.
  ☆29Updated 4 years ago
• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆38Updated 5 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆128Updated last year
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆46Updated 3 months ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆46Updated last year
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 6 months ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆32Updated last year
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆38Updated last year
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆33Updated 3 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆122Updated 7 months ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 7 months ago
• thu-cs-lab / Digital-Design-Docs
  Documentation for Digital Design course
  ☆19Updated last week
• OSCPU / yosys-sta
  ☆53Updated last month
• MaZirui2001 / Zircon
  ☆23Updated 3 weeks ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 11 months ago
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆49Updated 3 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆56Updated 3 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆28Updated 10 months ago
• USTC-vlab / docs
  USTC Vlab 远程教学云桌面平台的使用文档
  ☆44Updated last week
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆48Updated 4 years ago
• iFuProcessor / iFuCore
  ☆15Updated 6 months ago