Alternatives and similar repositories for antikc

Users that are interested in antikc are comparing it to the libraries listed below

• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆24Updated 6 years ago
• muhammadaldacher / Analog-design-of-4-bit-current-steering-DACs
  This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…
  ☆17Updated 4 months ago
• mbits-mirafra / i3c_avip
  Verification IP project for I3C protocol
  ☆20Updated 6 months ago
• pbridd / lzrw1-compression-core
  This is the repository for a verilog implementation of a lzrw1 compression core
  ☆18Updated 7 years ago
• Kocha / systemverilog
  SystemVerilog Example Files
  ☆11Updated 12 years ago
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆14Updated last month
• Minres / SystemC-Quickstart
  A simple C++ CMake project to jump-start development of SystemC models and systems
  ☆28Updated 10 months ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated 10 months ago
• bluecheetah / cbag
  A C++ VLSI circuit schematic and layout database library
  ☆14Updated last year
• andrewandrepowell / zybo_petalinux
  Small projects intended to run on the Digilent Zybo development board, utilizing PetaLinux on the Zynq's ARM processor.
  ☆23Updated 9 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• tsnlab / npu
  ☆23Updated last year
• vsdip / vsdsram
  An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…
  ☆11Updated 5 years ago
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆21Updated 9 months ago
• eda-ricercatore / Lombardia-STIL
  A C++ -based STIL parser.
  ☆11Updated 4 years ago
• alexforencich / fpga-utils
  Various utilities for working with FPGAs
  ☆13Updated 9 years ago
• mvsoliveira / IBERTpy
  A Python package for running IBERT Eye scan in Vivado, ploting eye diagrams with mathplotlib and compiling results with LaTeX
  ☆14Updated 4 years ago
• kdurant / uvm_study
  study uvm step by step
  ☆10Updated 6 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆33Updated 5 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆30Updated last year
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆24Updated 5 years ago
• xyzxinyizhang / FPGA-SFP-communication-with-Aurora
  ☆20Updated 6 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated last year
• alexforencich / verilog-ft245
  Verilog FT245 to AXI stream interface
  ☆29Updated 7 years ago
• lnls-dig / general-cores
  general-cores
  ☆21Updated 2 months ago
• dcblack / sc-platform
  Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0
  ☆26Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆18Updated 7 years ago
• dpiegdon / verilog-can
  Verilog CAN controller that is compatible to the SJA 1000.
  ☆14Updated 4 years ago