blackmesalabs / MesaBusProtocolLinks
Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
☆33Updated 6 months ago
Alternatives and similar repositories for MesaBusProtocol
Users that are interested in MesaBusProtocol are comparing it to the libraries listed below
Sorting:
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated 3 weeks ago
- Misc open FPGA flow examples☆8Updated 5 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- Yosys Plugins☆21Updated 5 years ago
- Reusable Verilog 2005 components for FPGA designs☆44Updated 4 months ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Small footprint and configurable Inter-Chip communication cores☆59Updated 3 weeks ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 5 years ago
- iDEA FPGA Soft Processor☆16Updated 9 years ago
- ☆20Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Updated 7 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆21Updated 5 years ago
- Utilities for the ECP5 FPGA☆18Updated 3 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- USB virtual model in C++ for Verilog☆31Updated 8 months ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Simplified environment for litex☆14Updated 4 years ago
- ☆45Updated 2 years ago
- ☆16Updated 3 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 11 months ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- SDRAM controller with multiple wishbone slave ports☆29Updated 6 years ago