blackmesalabs / MesaBusProtocolLinks
Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
☆34Updated 8 months ago
Alternatives and similar repositories for MesaBusProtocol
Users that are interested in MesaBusProtocol are comparing it to the libraries listed below
Sorting:
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated last week
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆18Updated last month
- Wishbone controlled I2C controllers☆51Updated 8 months ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- ☆20Updated 3 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 6 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆95Updated 5 years ago
- Generic Logic Interfacing Project☆46Updated 5 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆43Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆91Updated 5 years ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/x393☆40Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆34Updated 5 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 9 years ago
- ☆45Updated 2 years ago
- USB Full Speed PHY☆45Updated 5 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆32Updated 4 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- VHDL PCIe Transceiver☆29Updated 5 years ago
- Triple Modular Redundancy☆27Updated 5 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Misc open FPGA flow examples☆8Updated 5 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆42Updated 2 years ago