Alternatives and similar repositories for 16-Bit-CPU-using-Verilog

Users that are interested in 16-Bit-CPU-using-Verilog are comparing it to the libraries listed below

• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆273Updated 4 months ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆133Updated 4 years ago
• martinKindall / risc-v-single-cycle
  A Single Cycle Risc-V 32 bit CPU
  ☆52Updated 2 weeks ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆397Updated last year
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆53Updated last year
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆159Updated last year
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 6 months ago
• abdelazeem201 / ASIC-Design-Roadmap
  The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…
  ☆400Updated 3 months ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆158Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆117Updated 2 weeks ago
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆119Updated 3 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆112Updated last year
• FPGADude / Digital-Design
  Verilog HDL files
  ☆153Updated last year
• y-C-x / HDLBits_Solution
  My solution to the problem set on HDLBits.
  ☆26Updated 5 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆176Updated last week
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆55Updated last year
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆259Updated 9 months ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆197Updated 3 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆136Updated 5 years ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆151Updated 4 years ago
• cameronshinn / tiny-tpu
  Small-scale Tensor Processing Unit built on an FPGA
  ☆203Updated 6 years ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆142Updated last week
• aseddin / ece_3300
  ECE 3300 HDL Code
  ☆58Updated 2 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆302Updated 8 months ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆119Updated 3 years ago
• EkthaReddy / RISC-V-Single-Cycle-Processor
  In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…
  ☆15Updated last year
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆145Updated 9 years ago
• MMujtabaRoohani / RISC-V-Processor
  A verilog based 5-stage pipelined RISC-V Processor code.
  ☆29Updated 5 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆80Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆460Updated 4 months ago