vaibruce / Image_Recognition_Using_CNN_In_VerilogLinks
This repository contains the implementation of an image recognition model using a Convolutional Neural Network (CNN). The primary goal of this project is to detect the number of times a specific test pattern appears in a given input image.
☆25Updated 6 months ago
Alternatives and similar repositories for Image_Recognition_Using_CNN_In_Verilog
Users that are interested in Image_Recognition_Using_CNN_In_Verilog are comparing it to the libraries listed below
Sorting:
- Instructions & Assignments for COD Lab - UE22EC352A☆4Updated 7 months ago
- Implementation of CNN using Verilog☆218Updated 7 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆546Updated 3 years ago
- 100 Days of RTL☆368Updated 10 months ago
- Verilog AXI stream components for FPGA implementation☆810Updated 3 months ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆711Updated 7 months ago
- cocotb: Python-based chip (RTL) verification☆2,013Updated this week
- Solutions to HDLBits Verilog Problem Set☆25Updated this week
- AMBA bus lecture material☆441Updated 5 years ago
- Single Cycle MIPS Pipelined Processor using Verilog☆14Updated 3 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆352Updated last month
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆255Updated 3 weeks ago
- ☆688Updated this week
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆353Updated last year
- ☆111Updated last year
- Awesome ASIC design verification☆307Updated 3 years ago
- Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.☆934Updated 5 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,310Updated this week
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆353Updated last year
- 2D discrete cosine transform (DCT) of an 8x8 image in verilog HDL☆13Updated 2 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,300Updated last week
- Verilog AXI components for FPGA implementation☆1,746Updated 3 months ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆127Updated 4 years ago
- Router 1x3 design and uvm verification testbach and coverage report☆12Updated 7 months ago
- This is the main repository for all the examples for the book Practical UVM☆196Updated 4 years ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆14Updated 5 months ago
- Source code repo for UVM Tutorial for Candy Lovers☆189Updated 8 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆203Updated last month
- uvm AXI BFM(bus functional model)☆248Updated 12 years ago
- IC implementation of Systolic Array for TPU☆251Updated 8 months ago