vaibruce / Image_Recognition_Using_CNN_In_VerilogLinks
This repository contains the implementation of an image recognition model using a Convolutional Neural Network (CNN). The primary goal of this project is to detect the number of times a specific test pattern appears in a given input image.
☆25Updated last year
Alternatives and similar repositories for Image_Recognition_Using_CNN_In_Verilog
Users that are interested in Image_Recognition_Using_CNN_In_Verilog are comparing it to the libraries listed below
Sorting:
- Source Code for Sigma Web Development Course☆10,703Updated last year
- Master React.js, the most popular JavaScript library for building dynamic and responsive user interfaces. Learn component-based architect…☆20Updated 2 weeks ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆22Updated 4 months ago
- Verilog AXI components for FPGA implementation☆1,882Updated 9 months ago
- ☆14Updated 2 years ago
- This Repo contains the Source code of ATB7x learning☆14Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,437Updated last week
- ☆16Updated 7 months ago
- ☆16Updated 6 months ago
- 32-bit Superscalar RISC-V CPU☆1,147Updated 4 years ago
- Verilog PCI express components☆1,482Updated last year
- ☆15Updated 2 years ago
- Verilog AXI stream components for FPGA implementation☆844Updated 9 months ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆26Updated 11 months ago
- Make your first PR request! And enter the world of Open Source Contributions 🍉☆3,429Updated 4 months ago
- Must-have verilog systemverilog modules☆1,890Updated 4 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,152Updated 6 months ago
- AMBA bus lecture material☆489Updated 5 years ago
- ☆747Updated last week
- Contains the code examples from The UVM Primer Book sorted by chapters.☆588Updated 3 years ago
- Verilog library for ASIC and FPGA designers☆1,376Updated last year
- Various HDL (Verilog) IP Cores☆852Updated 4 years ago
- training labs and examples☆439Updated 3 years ago
- uvm_starter is a simple template for starting uvm projects☆11Updated 10 months ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆1,028Updated 2 weeks ago
- synthesiseable ieee 754 floating point library in verilog☆701Updated 2 years ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆367Updated 2 years ago
- RISC-V CPU Core (RV32IM)☆1,596Updated 4 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆628Updated last week
- 100 Days of RTL☆403Updated last year