Alternatives and similar repositories for uvm-tutorial-for-candy-lovers:

Users that are interested in uvm-tutorial-for-candy-lovers are comparing it to the libraries listed below

• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆147Updated 4 years ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆260Updated 2 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆183Updated 4 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆126Updated 6 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆166Updated 6 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆240Updated 11 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆101Updated 2 months ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆138Updated 6 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆111Updated 7 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆122Updated 2 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆93Updated 7 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆119Updated 3 years ago
• raysalemi / Python4RTLVerification
  ☆150Updated 2 years ago
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆100Updated 11 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆81Updated 3 months ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆287Updated 3 years ago
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆81Updated 3 years ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆83Updated 8 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆250Updated last month
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆194Updated last year
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆125Updated 3 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆387Updated 8 months ago
• dovstamler / uvm_agents
  UVM agents
  ☆78Updated 7 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆517Updated 3 years ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆72Updated 4 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆109Updated 10 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆85Updated last year
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆71Updated 3 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆38Updated 4 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆41Updated 3 years ago