upscale-project / aqed-dac2020-resultsLinks
Source files to reproduce the results shown for A-QED at DAC 2020
☆8Updated 4 years ago
Alternatives and similar repositories for aqed-dac2020-results
Users that are interested in aqed-dac2020-results are comparing it to the libraries listed below
Sorting:
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆17Updated 2 years ago
- Optimization results for superconducting electronic (SCE) circuits☆14Updated last year
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆34Updated 8 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆85Updated last year
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆35Updated 5 months ago
- Fast Symbolic Repair of Hardware Design Code☆25Updated 5 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆106Updated 2 months ago
- A RISC-V RV32 model ready for SMT program synthesis.☆11Updated 4 years ago
- Running Linux on IOb-SoC-OpenCryptoHW☆14Updated 11 months ago
- IDEA project source files☆107Updated 8 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆180Updated 5 years ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last week
- ☆174Updated 4 months ago
- NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…☆17Updated 4 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- ☆10Updated 5 years ago
- ☆12Updated 10 months ago
- A Modeling and Verification Platform for SoCs using ILAs☆78Updated last year
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- A logic synthesis tool☆74Updated last week
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆14Updated 5 months ago
- Branch Predictor Optimization for BlackParrot☆15Updated last year
- A tool for synthesizing Verilog programs☆95Updated last week
- All Digital Phase-Locked Loop (ADPLL)☆13Updated last year
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆13Updated 3 weeks ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆34Updated last year