tinyvision-ai-inc / Hands-on-FPGA-class

Related projects ⓘ

Alternatives and complementary repositories for Hands-on-FPGA-class

• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆88Updated 4 months ago
• fjullien / migen_litex_tutorials
  ☆97Updated last year
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆157Updated 8 months ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆79Updated 4 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆73Updated 2 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆90Updated 3 years ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆165Updated 3 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆48Updated this week
• ATaylorCEngFIET / introduction_to_vivado
  ☆17Updated last year
• openXC7 / demo-projects
  Demo projects for various Kintex FPGA boards
  ☆47Updated 5 months ago
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆141Updated last week
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated last year
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆122Updated 10 months ago
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆63Updated this week
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆40Updated last year
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆66Updated this week
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆116Updated 4 years ago
• ShawnHymel / introduction-to-fpga
  ☆155Updated 2 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆82Updated 6 years ago
• PacktPublishing / The-FPGA-Programming-Handbook-Second-Edition
  Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
  ☆52Updated last month
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆65Updated this week
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆47Updated 11 months ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆108Updated last month
• icebreaker-fpga / icebreaker-verilog-examples
  This repository contains small example designs that can be used with the open source icestorm flow.
  ☆140Updated 3 years ago
• olofk / vidbo
  Virtual Development Board
  ☆58Updated 2 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆68Updated 11 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆74Updated last month
• aignacio / mpsoc_example
  ☆57Updated 3 years ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆45Updated last month
• HDLForBeginners / Toolbox
  ☆55Updated 3 months ago