tinyvision-ai-inc / Hands-on-FPGA-classLinks
☆45Updated 2 years ago
Alternatives and similar repositories for Hands-on-FPGA-class
Users that are interested in Hands-on-FPGA-class are comparing it to the libraries listed below
Sorting:
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆93Updated 9 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆105Updated 10 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- End-to-End Open-Source I2C GPIO Expander☆31Updated 2 months ago
- Virtual Development Board☆60Updated 3 years ago
- A pipelined RISC-V processor☆57Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- Submission template for Tiny Tapeout 7 - Verilog HDL Projects☆19Updated last year
- ☆72Updated 10 months ago
- ☆110Updated 2 years ago
- ☆59Updated 3 years ago
- Verilog and VHDL for book☆82Updated last year
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆38Updated 3 weeks ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆89Updated this week
- Example of how to get started with olofk/fusesoc.☆17Updated 3 years ago
- ☆69Updated 9 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆170Updated last year
- Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt☆90Updated last month
- Documenting the Lattice ECP5 bit-stream format.☆54Updated 2 years ago
- A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …☆44Updated last year
- Arduino compatible Risc-V Based SOC☆150Updated 10 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆60Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆93Updated last year
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆132Updated 3 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆98Updated 2 years ago
- ☆23Updated last year
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆59Updated 6 months ago