Alternatives and similar repositories for getting-started-with-fpgas:

Users that are interested in getting-started-with-fpgas are comparing it to the libraries listed below

• HDLForBeginners / Examples
  ☆84Updated last year
• PacktPublishing / The-FPGA-Programming-Handbook-Second-Edition
  Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
  ☆60Updated 3 months ago
• HDLForBeginners / Toolbox
  ☆60Updated 5 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆57Updated last month
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆74Updated this week
• ShawnHymel / introduction-to-fpga
  ☆161Updated 2 years ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆93Updated 5 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆48Updated last year
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆77Updated 4 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆43Updated last year
• PacktPublishing / Learn-FPGA-Programming
  Learn FPGA Programming, published by Packt
  ☆182Updated 7 months ago
• ICE-V-Wireless / ICE-V-Wireless
  Combined ESP32C3 and iCE40 FPGA board
  ☆63Updated 2 weeks ago
• jogeshsingh / Learning-about-FPGA-DESIGN-
  This repository contains some introductory level review about learning about FPGA Design including some tutorials, links to websites and …
  ☆31Updated last month
• nandland / nandland
  All code found on nandland is here. underconstruction.gif
  ☆320Updated 2 years ago
• icebreaker-fpga / icebreaker-verilog-examples
  This repository contains small example designs that can be used with the open source icestorm flow.
  ☆143Updated 3 years ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆82Updated 4 years ago
• openXC7 / demo-projects
  Demo projects for various Kintex FPGA boards
  ☆48Updated 7 months ago
• nand2mario / usb_hid_host
  A compact USB HID host FPGA core supporting keyboards, mice and gamepads.
  ☆115Updated 5 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆131Updated this week
• ATaylorCEngFIET / CrowdSupplyWorkShop1
  ☆13Updated 3 years ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆48Updated this week
• galacticstudios / KiCadVerilog
  Generate Verilog code from a KiCad netlist
  ☆56Updated 2 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆104Updated 3 years ago
• efabless / clear
  ☆58Updated 4 months ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆168Updated last month
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆76Updated last year
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆161Updated 10 months ago
• mbalestrini / gds2gcode
  ☆23Updated last year
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆64Updated 6 months ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆37Updated last year