Alternatives and similar repositories for getting-started-with-fpgas

Users that are interested in getting-started-with-fpgas are comparing it to the libraries listed below

• PacktPublishing / The-FPGA-Programming-Handbook-Second-Edition
  Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
  ☆89Updated last month
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆43Updated last year
• HDLForBeginners / Examples
  ☆93Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆91Updated 2 weeks ago
• jogeshsingh / Learning-about-FPGA-DESIGN-
  This repository contains some introductory level review about learning about FPGA Design including some tutorials, links to websites and …
  ☆34Updated last month
• HDLForBeginners / Toolbox
  ☆71Updated 9 months ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆58Updated 6 months ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆104Updated 4 years ago
• viktor-nikolov / MicroBlaze-DDR3-tutorial
  Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
  ☆48Updated 11 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆128Updated 3 years ago
• PacktPublishing / Learn-FPGA-Programming
  Learn FPGA Programming, published by Packt
  ☆192Updated 11 months ago
• efard / DSPHDL
  ☆41Updated last year
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆88Updated last year
• sscs-ose / sscs-ose-chipathon.github.io
  ☆79Updated 4 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆46Updated last year
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆48Updated 3 months ago
• ShawnHymel / introduction-to-fpga
  ☆172Updated 3 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated last week
• projf / fpgatools
  Tools for FPGA development.
  ☆45Updated 2 years ago
• Obijuan / RISC-V-FPGA
  RISC-V CPU for OpenFPGAs, in Icestudio
  ☆91Updated 11 months ago
• bmurmann / EE628
  EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)
  ☆155Updated last month
• martinKindall / mips_cpu
  Single Cycle 32 bit MIPS
  ☆20Updated 2 years ago
• Manish4403 / RISC_V_with_ICACHE
  ☆13Updated 5 months ago
• VardhanSuroshi / VLSI-Physical-Design-Flow
  This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of …
  ☆11Updated last year
• ATaylorCEngFIET / introduction_to_vivado
  ☆20Updated 2 years ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆127Updated 9 months ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆76Updated last year
• adonairc / tt07-dda-van-der-pol
  DDA solver for the van der Pol oscillator using 16-bit posits
  ☆28Updated 3 months ago
• rodrigomelo9 / FOSS-for-FPGAs
  A getting started presentation (with examples) about how to use FLOSS for FPGA development.
  ☆35Updated last year
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆91Updated 8 months ago