nandland / getting-started-with-fpgasLinks
Verilog and VHDL for book
☆100Updated last year
Alternatives and similar repositories for getting-started-with-fpgas
Users that are interested in getting-started-with-fpgas are comparing it to the libraries listed below
Sorting:
- ☆180Updated 3 years ago
- Learn FPGA Programming, published by Packt☆192Updated last year
- Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt☆96Updated 4 months ago
- All code found on nandland is here. underconstruction.gif☆343Updated 3 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆143Updated 4 years ago
- ☆72Updated last year
- ☆99Updated last year
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆107Updated last year
- ☆49Updated 2 years ago
- Submission template for Tiny Tapeout 10 - Verilog HDL Projects☆24Updated 2 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆53Updated last year
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆63Updated 9 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆48Updated last year
- Example LED blinking project for your FPGA dev board of choice☆180Updated 2 weeks ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆175Updated last year
- A pipelined RISC-V processor☆57Updated last year
- This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…☆214Updated 2 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆108Updated last week
- Demo projects for various Kintex FPGA boards☆61Updated 3 months ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆119Updated 4 years ago
- [BRH YT CHANNEL] This repo contains all the code and ressources you need for the Zynq tutorials, ready to copy and paste.☆60Updated last month
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆94Updated last week
- Example of how to get started with olofk/fusesoc.☆17Updated 4 years ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆80Updated last week
- SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cycl…☆38Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆105Updated this week
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆139Updated 3 months ago
- RISC-V CPU for OpenFPGAs, in Icestudio☆93Updated last year
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆156Updated last year
- FPGA based microcomputer sandbox for software and RTL experimentation☆66Updated last week