Alternatives and similar repositories for parallella-fpga

Users that are interested in parallella-fpga are comparing it to the libraries listed below

• ZipCPU / s6soc
  CMod-S6 SoC
  ☆42Updated 7 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆64Updated this week
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆58Updated last week
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated last week
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆31Updated 4 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆34Updated 3 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆60Updated 6 years ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 2 months ago
• m-labs / nmigen-boards
  Board and connector definition files for nMigen
  ☆30Updated 4 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆54Updated 2 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆42Updated last week
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• bunnie / netv2-fpga-basic-overlay
  Vivado design for basic NeTV2 FPGA with chroma-based overlay
  ☆20Updated 8 years ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆97Updated 2 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• Kirill888 / parallella-fpga-dummy-io
  Sample minimal Vivado project for Parallella FPGA
  ☆42Updated 9 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆83Updated last year
• enjoy-digital / litex_vexriscv_smp_test
  VexRiscv-SMP integration test with LiteX.
  ☆25Updated 4 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆80Updated 3 years ago
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆45Updated 5 months ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆46Updated 4 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago