Alternatives and similar repositories for RISC-V-FPGA:

Users that are interested in RISC-V-FPGA are comparing it to the libraries listed below

• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆168Updated last month
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆152Updated 9 months ago
• FPGAwars / FPGA-peripherals
  Collection of open-source peripherals in Verilog
  ☆173Updated 2 years ago
• davidthings / tinyfpga_bx_usbserial
  USB Serial on the TinyFPGA BX
  ☆135Updated 3 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆169Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆124Updated 3 weeks ago
• ldoolitt / vhd2vl
  ☆124Updated last month
• mattvenn / basic-ecp5-pcb
  Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
  ☆102Updated 3 years ago
• HDLForBeginners / Examples
  ☆84Updated last year
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆134Updated last year
• emard / ulx3s-misc
  Miscellaneous ULX3S examples (advanced)
  ☆75Updated last year
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆124Updated last year
• FPGAwars / Alhambra-II-FPGA
  Alhambra II FPGA board
  ☆87Updated 2 months ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆109Updated 3 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆74Updated this week
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆93Updated 5 months ago
• RadionaOrg / ulx3s-links
  List of all links you can try with ULX3S
  ☆95Updated 3 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆83Updated 6 years ago
• olofk / corescore
  CoreScore
  ☆142Updated 4 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆86Updated 3 months ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆65Updated 3 years ago
• ulx3s / fpga-odysseus
  FPGA Odysseus with ULX3S
  ☆64Updated last year
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆67Updated this week
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆271Updated 9 months ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆148Updated 6 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆67Updated 2 years ago
• lawrie / tiny_usb_examples
  Using the TinyFPGA BX USB code in user designs
  ☆49Updated 5 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆44Updated last year
• icebreaker-fpga / icebreaker-verilog-examples
  This repository contains small example designs that can be used with the open source icestorm flow.
  ☆143Updated 3 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆72Updated 2 years ago