supranational / vdf-fpgaLinks
Implementation of an RSA VDF evaluator targeting FPGAs.
☆49Updated 6 years ago
Alternatives and similar repositories for vdf-fpga
Users that are interested in vdf-fpga are comparing it to the libraries listed below
Sorting:
- Zcash FPGA acceleration engine☆131Updated 5 years ago
- Low level arithmetic primitives in RTL☆23Updated 5 years ago
- XCrypto: a cryptographic ISE for RISC-V☆92Updated 2 years ago
- Example verilog / miner for crypto mining using AWS F1 instances☆30Updated 7 years ago
- An acceleration engine for proving SNARKS over the bn128 curve, targeted for AWS FPGAs☆58Updated 5 years ago
- Elgamal's over Elliptic Curves☆19Updated 7 years ago
- Cryptonight Monero Verilog code for ASIC☆20Updated 7 years ago
- A Hardware Implemented Poseidon Hasher☆19Updated 3 years ago
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆83Updated 7 years ago
- Hardware implementation of ORAM☆24Updated 8 years ago
- FPGA referrence implementation for aion equihash 2109☆15Updated 7 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆37Updated 4 years ago
- Defense/Attack PUF Library (DA PUF Library)☆54Updated 5 years ago
- ☆47Updated 5 years ago
- A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…☆176Updated 3 years ago
- Verilog implementation of the 32-bit version of the Blake2 hash function☆21Updated last week
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆136Updated 3 years ago
- Simple hash table on Verilog (SystemVerilog)☆50Updated 9 years ago
- ☆27Updated 10 months ago
- A collection of core generators to use with FuseSoC☆17Updated last year
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Updated 8 months ago
- Hardware implementation of the blake2 hash function☆25Updated 5 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆31Updated 7 years ago
- Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board☆15Updated 3 years ago
- ☆25Updated 4 years ago
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆90Updated 6 years ago
- Mining CryptoNight Haven on the Varium C1100☆10Updated 3 years ago
- Random ideas and interesting ideas for things we hope to eventually do.☆86Updated 3 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (build-environment repo).☆11Updated 4 years ago