Alternatives and similar repositories for CIC:

Users that are interested in CIC are comparing it to the libraries listed below

• catkira / DDS
  HDL code for a DDS (direct digital synthesizer) with AXI stream interface
  ☆18Updated last year
• catkira / complex_multiplier
  HDL code for a complex multiplier with AXI stream Interface
  ☆13Updated last year
• Victoromoniyi / gr-litex
  LiteX Accelerator Block for GNU Radio
  ☆24Updated 3 years ago
• oscimp / oscimpDigital
  OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing
  ☆53Updated last week
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆23Updated last year
• efard / DSPHDL
  ☆41Updated last year
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆21Updated last month
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 3 weeks ago
• yrrapt / caravel_amsat_txrx_ic
  ☆30Updated 4 years ago
• suoto / fpga_cores
  ☆33Updated last year
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆72Updated 3 years ago
• B0WEN-HU / gr-verilog
  This is an OOT module for GNU Radio integrating verilog simulation feature
  ☆38Updated 5 years ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆86Updated 6 months ago
• strath-sdr / pynq_agc
  Demonstration of Automatic Gain Control with PYNQ
  ☆12Updated 2 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• MorrisMA / 1PPS-DPLL
  DPLL for phase-locking to 1PPS signal
  ☆31Updated 8 years ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆27Updated 2 months ago
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆46Updated last year
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆12Updated 5 months ago
• Cognoscan / BoostDSP
  VHDL Library for implementing common DSP functionality.
  ☆27Updated 6 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆27Updated last year
• strath-sdr / rfsoc_notebooks
  A collection of RFSoC introductory notebooks for PYNQ.
  ☆19Updated 3 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆81Updated 2 years ago
• HarmonInstruments / verilog
  ☆20Updated 2 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆43Updated 9 years ago
• OpenResearchInstitute / dvb_fpga
  RTL implementation of components for DVB-S2
  ☆114Updated last year
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆24Updated 3 weeks ago