catkira / CIC
HDL code for a complex multiplier with AXI stream interface
☆16Updated 2 years ago
Alternatives and similar repositories for CIC:
Users that are interested in CIC are comparing it to the libraries listed below
- HDL code for a complex multiplier with AXI stream Interface☆13Updated 2 years ago
- HDL code for a DDS (direct digital synthesizer) with AXI stream interface☆18Updated 2 years ago
- An RFSoC Frequency Planner developed using Python.☆27Updated last year
- OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing☆54Updated last month
- JESD204B core for Migen/MiSoC☆36Updated 4 years ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆72Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 2 months ago
- Fixed-point math library with VHDL, Python and MATLAB support☆22Updated 2 months ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Updated 5 years ago
- LiteX Accelerator Block for GNU Radio☆24Updated 3 years ago
- ☆32Updated 2 years ago
- Demonstration of Automatic Gain Control with PYNQ☆13Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆57Updated this week
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- ☆41Updated last year
- ☆30Updated 4 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆85Updated 2 years ago
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆43Updated 3 years ago
- Small footprint and configurable JESD204B core☆42Updated 2 weeks ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆45Updated 3 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆21Updated 3 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆48Updated last year
- Extensible FPGA control platform☆60Updated 2 years ago
- DPLL for phase-locking to 1PPS signal☆32Updated 8 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆18Updated 5 months ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆43Updated last year
- VHDL Library for implementing common DSP functionality.☆27Updated 6 years ago