catkira / DDSLinks
HDL code for a DDS (direct digital synthesizer) with AXI stream interface
☆22Updated 2 years ago
Alternatives and similar repositories for DDS
Users that are interested in DDS are comparing it to the libraries listed below
Sorting:
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆125Updated 4 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- assorted library of utility cores for amaranth HDL☆97Updated last year
- Small footprint and configurable JESD204B core☆49Updated last month
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆20Updated this week
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆86Updated 2 years ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆71Updated 4 years ago
- A basic Soft(Gate)ware Defined Radio architecture☆100Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆96Updated 5 years ago
- A collection of demonstration digital filters☆161Updated last year
- A collection of phase locked loop (PLL) related projects☆114Updated last year
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆111Updated 9 years ago
- HDL code for a complex multiplier with AXI stream Interface☆13Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated this week
- VHDL Library for implementing common DSP functionality.☆30Updated 7 years ago
- Delta Sigma DAC FPGA☆45Updated 9 months ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆76Updated 3 years ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆38Updated 9 months ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated 6 months ago
- An RFSoC Frequency Planner developed using Python.☆31Updated 2 years ago
- Wishbone controlled I2C controllers☆55Updated last year
- Small footprint and configurable Inter-Chip communication cores☆66Updated last month
- ☆33Updated 2 years ago
- Nitro USB FPGA core☆85Updated last year
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆91Updated 5 months ago
- VHDL PCIe Transceiver☆31Updated 5 years ago