catkira / DDSLinks
HDL code for a DDS (direct digital synthesizer) with AXI stream interface
☆24Updated 2 years ago
Alternatives and similar repositories for DDS
Users that are interested in DDS are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable JESD204B core☆50Updated 2 weeks ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆127Updated 4 years ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆73Updated 4 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆39Updated 11 months ago
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆22Updated this week
- JESD204b modules in VHDL☆30Updated 6 years ago
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆114Updated last week
- Extensible FPGA control platform☆61Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆116Updated 2 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆76Updated 3 years ago
- A collection of demonstration digital filters☆165Updated 2 years ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆86Updated 3 years ago
- VHDL Library for implementing common DSP functionality.☆31Updated 7 years ago
- assorted library of utility cores for amaranth HDL☆100Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Updated 5 years ago
- ☆33Updated 2 years ago
- DPLL for phase-locking to 1PPS signal☆34Updated 9 years ago
- An RFSoC Frequency Planner developed using Python.☆32Updated 2 years ago
- Delta Sigma DAC FPGA☆47Updated 11 months ago
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆112Updated 9 years ago
- A series of CORDIC related projects☆121Updated last year
- Digital Interpolation Techniques Applied to Digital Signal Processing☆67Updated last year
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Updated last year
- This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…☆72Updated 8 years ago
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated 8 months ago
- HDL code for a complex multiplier with AXI stream Interface☆13Updated 2 years ago
- ☆16Updated 4 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools