Alternatives and similar repositories for Universal_Verification_Methodology

Users that are interested in Universal_Verification_Methodology are comparing it to the libraries listed below

• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆289Updated 3 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆263Updated 12 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆443Updated last year
• Ummidichandrika / 100-Days-of-RTL
  ☆116Updated 2 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆154Updated 7 months ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆117Updated last year
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆204Updated 8 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆163Updated 3 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆136Updated 4 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆136Updated 8 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆160Updated 5 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆190Updated 7 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆341Updated 3 years ago
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆114Updated 11 years ago
• karribharathi / 100-Days-of-RTL
  ☆17Updated 2 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆74Updated 3 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆237Updated 2 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆215Updated 5 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆175Updated 2 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆597Updated 4 years ago
• raysalemi / Python4RTLVerification
  ☆174Updated 3 years ago
• TheRA1A / Router1x3
  Router 1x3 design and uvm verification testbach and coverage report
  ☆12Updated last year
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆446Updated 3 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆45Updated last year
• bpvsr / 2_Interview_Questions
  # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…
  ☆24Updated 6 months ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆406Updated last year
• KOTHAVANI / 100-Days-of-RTL-code
  ☆44Updated 2 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆160Updated 7 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆104Updated 2 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆497Updated this week