silverjam / VHDLLinks
VHDL Samples
☆69Updated 12 years ago
Alternatives and similar repositories for VHDL
Users that are interested in VHDL are comparing it to the libraries listed below
Sorting:
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆40Updated 9 years ago
- u-boot-xarm from xilinx git repo with Digilent additions☆32Updated last year
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- An Open Source configuration of the Arty platform☆130Updated last year
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆195Updated 6 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆57Updated 3 months ago
- Collection of open-source peripherals in Verilog☆179Updated 3 years ago
- Collection of hardware description languages writings and code snippets☆27Updated 10 years ago
- Migrated to Codeberg☆92Updated 8 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆35Updated 3 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆154Updated 7 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆18Updated 8 months ago
- The OpenRISC 1000 architectural simulator☆76Updated 3 months ago
- CMod-S6 SoC☆42Updated 7 years ago
- Image Processing on FPGA using VHDL☆41Updated 11 years ago
- Verilog implementation of a RISC-V core☆123Updated 6 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 9 years ago
- Ethernet MAC 10/100 Mbps☆85Updated 5 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated 11 months ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah…☆41Updated 7 months ago
- Another tiny RISC-V implementation☆57Updated 4 years ago
- turbo 8051☆29Updated 7 years ago
- PulseRain Rattlesnake - RISCV RV32IMC Soft CPU☆34Updated 5 years ago
- Library of VHDL components that are useful in larger designs.☆235Updated last year
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆102Updated 6 years ago