silverjam / VHDLLinks
VHDL Samples
☆70Updated 12 years ago
Alternatives and similar repositories for VHDL
Users that are interested in VHDL are comparing it to the libraries listed below
Sorting:
- An Open Source configuration of the Arty platform☆131Updated 2 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆41Updated 10 years ago
- Collection of open-source peripherals in Verilog☆183Updated 3 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- CMod-S6 SoC☆45Updated 8 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- FPGA implementation of the 8051 Microcontroller (Verilog)☆52Updated 11 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆19Updated last year
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆71Updated 7 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 10 years ago
- Collection of hardware description languages writings and code snippets☆28Updated 10 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆37Updated 3 years ago
- turbo 8051☆29Updated 8 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆32Updated 5 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆160Updated 7 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated last year
- Implemetation of pipelined ARM7TDMI processor in Verilog☆93Updated 7 years ago
- Another tiny RISC-V implementation☆64Updated 4 years ago
- The OpenRISC 1000 architectural simulator☆77Updated 8 months ago
- ☆63Updated 7 years ago
- Verilog uart receiver and transmitter modules for De0 Nano☆18Updated 11 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆91Updated 5 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- Wishbone interconnect utilities☆44Updated last month
- ☆27Updated 7 years ago
- Featherweight RISC-V implementation☆53Updated 4 years ago