Expiremental Speech Recognition System using VHDL & MATLAB.
☆50Mar 18, 2018Updated 8 years ago
Alternatives and similar repositories for FPGA-Speech-Recognition
Users that are interested in FPGA-Speech-Recognition are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆30Dec 10, 2021Updated 4 years ago
- FPGA FAST image feature detector implementation in VHDL☆38Nov 14, 2022Updated 3 years ago
- ☆12Aug 12, 2020Updated 5 years ago
- ☆17Jun 13, 2022Updated 3 years ago
- Design and implementation of a reconfigurable FIR filter in FPGA☆15Sep 26, 2022Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A CIC filter implemented in Verilog☆24Sep 7, 2015Updated 10 years ago
- Connecting FPGA and MCU using Ethernet RMII☆23Jan 23, 2016Updated 10 years ago
- The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the N…☆29Feb 4, 2017Updated 9 years ago
- Simple UART controller for FPGA written in VHDL☆106Aug 7, 2021Updated 4 years ago
- MSP430F5529 Code Example☆12Jun 20, 2018Updated 7 years ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 8 months ago
- Programming Language for everyone, and no one.☆19Feb 13, 2018Updated 8 years ago
- A Pong game written in VHDL using a Xilinx Spartan 3 board. VGA + PS/2 Keyboard + Sound support.☆22Nov 7, 2015Updated 10 years ago
- JSynthLib is an Open Source Universal Synthesizer Patch Editor / Librarian☆12Feb 28, 2009Updated 17 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- MIPS processor designed in VHDL☆56Aug 24, 2015Updated 10 years ago
- VLSI VS1053b DSP Audio Processor Example Projects and Resources☆11Jan 17, 2018Updated 8 years ago
- Arduino library to support the VL53L0X Time-of-Flight and gesture-detection sensor☆19Nov 15, 2021Updated 4 years ago
- FPGA implementation of Real-time Ethernet communication using RMII Interface☆14Sep 18, 2014Updated 11 years ago
- audio DSP applications using zynq/zed boards☆22Jul 24, 2020Updated 5 years ago
- ☆12Jun 13, 2017Updated 8 years ago
- ☆10Jul 7, 2022Updated 3 years ago
- Verilog implementation of a ultrasonic radar☆19Jan 7, 2018Updated 8 years ago
- Hey guys this the project where i have implemented the Kalman filter for MPPT for solar PV module☆20Nov 8, 2017Updated 8 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- A collection of VHDL projects for generating VGA output☆25Nov 26, 2018Updated 7 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 6 years ago
- ☆24Oct 20, 2023Updated 2 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- ☆10Apr 18, 2017Updated 9 years ago
- PS/2 Keyboard IP written in VHDL for Xilinx FPGA☆17Jul 11, 2015Updated 10 years ago
- Code repository for my degree project on FS sonar SLAM.☆10Feb 24, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A repository of IPs for hardware computer vision (FPGA)☆98Oct 21, 2015Updated 10 years ago
- Python FIR Filter Package for Xilinx Pynq Board☆30Apr 5, 2018Updated 8 years ago
- USB Full Speed PHY☆49May 3, 2020Updated 5 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- This code is to implement the model-free control algorithm as introduced in the paper Model-free control by Michel Fliess and Cedric Join…☆13Nov 29, 2017Updated 8 years ago
- Edit SystemVerilog files (and UVM files) in Vim/gVim☆30Mar 8, 2024Updated 2 years ago
- ☆11Jan 23, 2017Updated 9 years ago