Alternatives and similar repositories for ahb3lite_timer:

Users that are interested in ahb3lite_timer are comparing it to the libraries listed below

• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆39Updated 11 months ago
• IObundle / iob-eth
  Basic Verilog Ethernet core and C driver functions
  ☆11Updated last month
• RoaLogic / ahb3lite_memory
  Multi-Technology RAM with AHB3Lite interface
  ☆23Updated 11 months ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated 11 months ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆48Updated 5 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆40Updated last year
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆65Updated 3 months ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 10 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆42Updated 4 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆33Updated 9 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆17Updated 4 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆18Updated 2 years ago
• ShonTaware / LowPower
  Various low power labs using sky130
  ☆12Updated 3 years ago
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆16Updated 5 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 6 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆31Updated 2 months ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆27Updated 2 years ago
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆14Updated 10 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆36Updated 3 years ago