secworks / blake2
Hardware implementation of the blake2 hash function
☆25Updated 4 years ago
Alternatives and similar repositories for blake2
Users that are interested in blake2 are comparing it to the libraries listed below
Sorting:
- An open source FPGA miner for Blakecoin☆51Updated 10 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Updated 5 years ago
- Hardware implementation of the SipHash short-inout PRF☆17Updated last month
- A VHDL implementation of SipHash☆13Updated 10 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆39Updated 9 years ago
- Axiom Alpha prototype software (FPGA, Linux, etc.)☆29Updated 9 years ago
- IP submodules, formatted for easier CI integration☆29Updated last year
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 5 months ago
- ☆9Updated 2 years ago
- A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open d…☆173Updated 3 years ago
- Verilog 2001 implementation of the ChaCha stream cipher.☆40Updated last month
- XCrypto: a cryptographic ISE for RISC-V☆93Updated 2 years ago
- SDK for Keystone Enclave - ABI/SBI libraries and sample apps☆44Updated 2 years ago
- ☆63Updated 6 years ago
- Verilog implementation of the SHA-512 hash function.☆38Updated last month
- Vivado design for basic NeTV2 FPGA with chroma-based overlay☆20Updated 8 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆78Updated 7 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- Zephyr port to riscv architecture☆24Updated 7 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready☆35Updated 4 years ago
- VexRiscv-SMP integration test with LiteX.☆25Updated 4 years ago
- Bitcoin miner for Xilinx FPGAs☆97Updated 11 years ago
- 586 compatible soft core for FPGA in verilog with AXI4 interface☆14Updated 8 years ago
- Verilog implementation of the 32-bit version of the Blake2 hash function☆21Updated last month
- Test of the USB3 IP Core from Daisho on a Xilinx device☆90Updated 5 years ago
- SNES for MiSTer☆15Updated 4 years ago
- Open Processor Architecture☆26Updated 9 years ago