secworks / blake2
Hardware implementation of the blake2 hash function
☆25Updated 4 years ago
Alternatives and similar repositories for blake2:
Users that are interested in blake2 are comparing it to the libraries listed below
- An open source FPGA miner for Blakecoin☆51Updated 10 years ago
- A VHDL implementation of SipHash☆13Updated 9 years ago
- IP submodules, formatted for easier CI integration☆29Updated last year
- Hardware implementation of the SipHash short-inout PRF☆17Updated 3 years ago
- Software, tools, documentation for Vegaboard platform☆63Updated 5 years ago
- Verilog 2001 implementation of the ChaCha stream cipher.☆39Updated 2 months ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆39Updated 9 years ago
- Verilog implementation of the 32-bit version of the Blake2 hash function☆21Updated last year
- A Qt5 based free VLSI development tool☆30Updated 6 years ago
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆77Updated 6 years ago
- XCrypto: a cryptographic ISE for RISC-V☆92Updated 2 years ago
- FPGA Development for the parallella☆19Updated 7 years ago
- Project X-Ray Database: XC7 Series☆65Updated 3 years ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆13Updated 5 years ago
- Vivado design for basic NeTV2 FPGA with chroma-based overlay☆20Updated 8 years ago
- Port of Arduino environment for Freedom E 300 Dev Kit & HiFive Board☆31Updated 5 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆54Updated 5 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆44Updated last month
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆34Updated 3 years ago
- FPGA config visualized. demo:☆19Updated 4 years ago
- Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready☆36Updated 3 years ago
- SNES for MiSTer☆15Updated 4 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated this week
- ☆34Updated 7 years ago
- Exploring the Ed25519 (FPGA) design space.☆16Updated 7 years ago
- Mining CryptoNight Haven on the Varium C1100☆10Updated 2 years ago
- Xilinx Bitstream Format Library. Easily read .bit files from C programs.☆13Updated 9 years ago
- 1st Testwafer for LibreSilicon☆15Updated 5 years ago
- SymbiFlow WIP changes for Yosys Open SYnthesis Suite☆37Updated 10 months ago
- ☆25Updated 6 years ago