sarachour / legno-compiler
a compiler for the Apollo project that targets the HCDCv2 Analog Device
☆30Updated 3 years ago
Alternatives and similar repositories for legno-compiler:
Users that are interested in legno-compiler are comparing it to the libraries listed below
- FPGA synthesis tool powered by program synthesis☆41Updated 2 months ago
- Time-sensitive affine types for predictable hardware generation☆138Updated 7 months ago
- ☆13Updated last year
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆89Updated 8 months ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆12Updated 3 years ago
- CoreIR Symbolic Analyzer☆64Updated 4 years ago
- PolyGen is a code generator for the polyhedral model, written and proved in Coq.☆10Updated 4 years ago
- ☆40Updated 3 years ago
- A Modeling and Verification Platform for SoCs using ILAs☆75Updated 7 months ago
- A core language for rule-based hardware design 🦑☆147Updated 4 months ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆146Updated 4 months ago
- PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow☆63Updated last year
- A generic test bench written in Bluespec☆49Updated 4 years ago
- ☆25Updated 3 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- The source code to the Voss II Hardware Verification Suite☆53Updated 2 weeks ago
- An advanced header-only exact synthesis library☆24Updated 2 years ago
- Verilog development and verification project for HOL4☆25Updated 3 months ago
- A circuit toolkit☆97Updated 4 years ago
- ☆23Updated 4 years ago
- ☆25Updated 2 years ago
- Formal specification and verification of hardware, especially for security and privacy.☆124Updated 2 years ago
- ILA Model Database☆22Updated 4 years ago
- Pono: A flexible and extensible SMT-based model checker☆91Updated last week
- Designs, infrastructure, and experiments around Race Logic☆23Updated 4 years ago
- ☆54Updated this week
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆99Updated 5 years ago
- A standalone structural (gate-level) verilog parser☆34Updated 2 months ago
- ☆13Updated 4 years ago
- Showcase examples for EPFL logic synthesis libraries☆192Updated 10 months ago