sarachour / legno-compilerLinks
a compiler for the Apollo project that targets the HCDCv2 Analog Device
☆29Updated 4 years ago
Alternatives and similar repositories for legno-compiler
Users that are interested in legno-compiler are comparing it to the libraries listed below
Sorting:
- RKQC is a compiler for reversible logic circuitry. The framework has been developed to compile high level circuit descriptions down to "Q…☆17Updated 9 years ago
- Time-sensitive affine types for predictable hardware generation☆145Updated last week
- FPGA synthesis tool powered by program synthesis☆52Updated last week
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆93Updated last month
- Search-based compiler for high-performance DSP programming☆68Updated 11 months ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆162Updated 2 months ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- ☆14Updated 2 years ago
- ☆40Updated 4 years ago
- Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"☆284Updated last year
- ☆26Updated 3 years ago
- Chunky Loop Analyzer: A Polyhedral Representation Extraction Tool for High Level Programs☆24Updated 2 years ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆70Updated 4 months ago
- A circuit toolkit☆105Updated 5 years ago
- Designs, infrastructure, and experiments around Race Logic☆25Updated 5 years ago
- A toy compiler for NumPy array expressions that uses e-graphs and MLIR☆107Updated 2 months ago
- A standard for floating point accuracy benchmarks☆53Updated 6 months ago
- A Parallel SAT Solver with GPU Accelerated Inprocessing☆129Updated 2 weeks ago
- Formal specification and verification of hardware, especially for security and privacy.☆126Updated 3 years ago
- A core language for rule-based hardware design 🦑☆161Updated 4 months ago
- Library to plot integer sets and maps☆53Updated 8 years ago
- Memory consistency modelling using Alloy☆31Updated 4 years ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- Integer Set Library (source repository: http://repo.or.cz/w/isl.git)☆71Updated 8 months ago
- State-of-the-art in reversible logic synthesis☆23Updated 9 years ago
- ☆26Updated 2 years ago
- A Hardware Pipeline Description Language☆47Updated 3 months ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 5 years ago
- BTOR2 MLIR project☆26Updated last year
- materials available to the public☆27Updated 2 months ago