Ekdohibs / PolyGen
PolyGen is a code generator for the polyhedral model, written and proved in Coq.
☆10Updated 4 years ago
Alternatives and similar repositories for PolyGen:
Users that are interested in PolyGen are comparing it to the libraries listed below
- FPGA synthesis tool powered by program synthesis☆41Updated this week
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆13Updated 4 months ago
- BTOR2 MLIR project☆25Updated last year
- ☆16Updated 3 years ago
- ☆12Updated 7 years ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆12Updated 4 years ago
- A translation validation framework for MLIR☆81Updated 3 weeks ago
- ☆40Updated 3 years ago
- ☆25Updated 2 years ago
- compiling DSLs to high-level hardware instructions☆22Updated 2 years ago
- A multicore microprocessor test harness for measuring interference☆14Updated 4 years ago
- Languages, Tools, and Techniques for Accelerator Design☆32Updated 3 years ago
- The source code to the Voss II Hardware Verification Suite☆56Updated 2 weeks ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆13Updated 2 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- Memory consistency modelling using Alloy☆29Updated 4 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆90Updated 9 months ago
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆11Updated 7 months ago
- Verilog AST☆21Updated last year
- outline and links for PLDI 2022 tutorial☆17Updated 2 years ago
- SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints☆25Updated 5 years ago
- ☆24Updated 4 years ago
- SMT-LIB benchmarks for shape computations from deep learning models in PyTorch☆17Updated 2 years ago
- Random Generator of Btor2 Files☆10Updated last year
- A Hardware Pipeline Description Language☆43Updated last year
- Search-based compiler for high-performance DSP programming☆63Updated 5 months ago
- Verilog development and verification project for HOL4☆26Updated 5 months ago
- CoreIR Symbolic Analyzer☆70Updated 4 years ago
- RTLCheck☆21Updated 6 years ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated 2 years ago