marg-tools / CoMeTLinks
An EDA toolchain for integrated core-memory interval thermal simulations of 2D, 2.5, and 3D multi-/many-core processors
☆50Updated last month
Alternatives and similar repositories for CoMeT
Users that are interested in CoMeT are comparing it to the libraries listed below
Sorting:
- Dataset for ML-guided Accelerator Design☆38Updated 9 months ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆52Updated last year
- An integrated CGRA design framework☆90Updated 5 months ago
- A list of our chiplet simulaters☆36Updated 2 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆52Updated 8 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated last month
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆58Updated last month
- ☆49Updated 2 months ago
- gem5 repository to study chiplet-based systems☆81Updated 6 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆84Updated 4 months ago
- CGRA Compilation Framework☆86Updated 2 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆27Updated 5 years ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆16Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- ACM TODAES Best Paper Award, 2022☆26Updated last year
- ☆24Updated last year
- Heterogeneous simulator for DECADES Project☆32Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆68Updated 5 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- CATCH 1.0, Initial full release of CATCH cost model.☆15Updated last month
- ☆87Updated last year
- An Open-Source Tool for CGRA Accelerators☆24Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆129Updated 5 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 3 years ago
- ☆63Updated 4 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago