Alternatives and similar repositories for riscv-smbios:

Users that are interested in riscv-smbios are comparing it to the libraries listed below

• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆42Updated 9 months ago
• XUANTIE-RV / xuantie-yocto
  Yocto project for Xuantie RISC-V CPU
  ☆38Updated 4 months ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆38Updated 6 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• SanDisk-Open-Source / riscv-fw-infrastructure
  Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...
  ☆52Updated 3 years ago
• lowRISC / rocket
  ☆31Updated 7 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆20Updated 5 years ago
• ultraembedded / altor32
  AltOr32 - Alternative Lightweight OpenRisc CPU
  ☆12Updated 9 years ago
• starfive-tech / opensbi
  ☆18Updated last month
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated 2 weeks ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆55Updated 5 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆74Updated last week
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• riscveval / Rocket-Chip
  ☆23Updated 7 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆40Updated 7 years ago
• enjoy-digital / litex_vexriscv_smp_test
  VexRiscv-SMP integration test with LiteX.
  ☆25Updated 4 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆47Updated 4 years ago
• ultraembedded / riscv32_linux_from_scratch
  RISC-V 32-bit Linux From Scratch
  ☆32Updated 4 years ago
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆28Updated 7 months ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 4 years ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• f4pga / f4pga
  Documentation for F4PGA
  ☆23Updated last year
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• bandvig / or1k_marocchino
  OpenRISC processor IP core based on Tomasulo algorithm
  ☆10Updated 3 years ago
• riscv / riscv-test-env
  ☆46Updated this week