Alternatives and similar repositories for riscv-smbios:

Users that are interested in riscv-smbios are comparing it to the libraries listed below

• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆38Updated 5 months ago
• starfive-tech / opensbi
  ☆18Updated 2 weeks ago
• ARM-software / bsa-acs
  Arm SystemReady : BSA Architecture Compliance Suite
  ☆24Updated this week
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆42Updated 9 months ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆55Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 weeks ago
• SanDisk-Open-Source / riscv-fw-infrastructure
  Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...
  ☆53Updated 3 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Updated 3 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆79Updated 4 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆74Updated 7 months ago
• XUANTIE-RV / xuantie-yocto
  Yocto project for Xuantie RISC-V CPU
  ☆38Updated 3 months ago
• f4pga / f4pga
  Documentation for F4PGA
  ☆23Updated last year
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• riscv / riscv-test-env
  ☆46Updated 2 weeks ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆63Updated 6 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• lowRISC / rocket
  ☆31Updated 7 years ago
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆21Updated 5 years ago
• lowRISC / lowrisc-toolchains
  UNSUPPORTED INTERNAL toolchain builds
  ☆37Updated last month
• openhwgroup / core-v-sw
  Main Repo for the OpenHW Group Software Task Group
  ☆17Updated last month
• tenstorrent / rv-core-dv-kit
  ☆24Updated last month
• riscv-mcu / riscv-gnu-toolchain
  GNU toolchain for RISC-V, including GCC. Tweaked for microcontrollers.
  ☆30Updated last month
• ultraembedded / altor32
  AltOr32 - Alternative Lightweight OpenRisc CPU
  ☆12Updated 9 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago