riscv / riscv-smbiosLinks
RISC-V SMBIOS Type 44 Spec
☆12Updated last year
Alternatives and similar repositories for riscv-smbios
Users that are interested in riscv-smbios are comparing it to the libraries listed below
Sorting:
- RISC-V Specific Device Tree Documentation☆42Updated 11 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- RISC-V Configuration Structure☆38Updated 7 months ago
- ☆18Updated last month
- Yocto project for Xuantie RISC-V CPU☆39Updated last month
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- The OpenRISC 1000 architectural simulator☆75Updated last month
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- Open Processor Architecture☆26Updated 9 years ago
- Main Repo for the OpenHW Group Software Task Group☆17Updated 3 months ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Port of EDK2 implementation of UEFI to RISC-V. See documentation at:☆18Updated 3 years ago
- 🌄 RISC-V Ecosystem Landscape: a living document that developers, investors, vendors, researchers and others can use as a resource on the…☆15Updated this week
- SiFive OpenEmbedded / Yocto BSP Layer☆52Updated last week
- ☆47Updated last month
- OmniXtend cache coherence protocol☆82Updated last week
- Xv6 ports for RISC-V☆10Updated 6 months ago
- RISC-V Frontend Server☆63Updated 6 years ago
- ☆17Updated last month
- GNU toolchain for RISC-V, including GCC. Tweaked for microcontrollers.☆30Updated 3 months ago
- An open standard Cache Coherent Fabric Interface repository☆66Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆56Updated 5 years ago
- ☆30Updated this week
- A design for TinyTapeout☆16Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- RISC-V Linux Port☆36Updated last week
- ☆32Updated 7 years ago
- ☆62Updated 4 years ago