Alternatives and similar repositories for gem5-triangel

Users that are interested in gem5-triangel are comparing it to the libraries listed below

• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆67Updated last year
• OpenXiangShan / GEM5
  ☆103Updated this week
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆32Updated 2 years ago
• kuczmmar / Runahead
  Running ahead of memory latency - Part II project
  ☆10Updated 2 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆44Updated 2 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆75Updated last month
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆12Updated 2 years ago
• cry-daniel / Computer-Architecture-Learning
  ☆65Updated 2 years ago
• miaochenlu / learn_prefetcher
  hardware & software prefetcher
  ☆28Updated last year
• JamesAslan / MicroArchBench
  ☆74Updated 11 months ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 4 months ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆158Updated this week
• OpenXiangShan / gsim
  ☆56Updated this week
• car3s / IPCP_ISCA2020
  Source codes for "Bouquet of Instruction Pointers"
  ☆17Updated 4 years ago
• dhschall / gem5-fdp
  Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5
  ☆25Updated this week
• xuefeng16 / Tyche-Artifact
  [TACO 2024] A hardware prefetching framework employing Tyche, a hardware prefetcher designed for indirect memory access patterns.
  ☆23Updated last year
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆21Updated 7 years ago
• shinezyy / gem5-official-old
  ☆20Updated 4 years ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆40Updated 4 months ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆123Updated 10 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆37Updated last year
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆92Updated 2 weeks ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆34Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated last year
• gem5bootcamp / gem5-bootcamp-env
  The gem5 Bootcamp 2022 environment. Archived.
  ☆35Updated last year