Alternatives and similar repositories for gem5-triangel

Users that are interested in gem5-triangel are comparing it to the libraries listed below

• OpenXiangShan / GEM5
  ☆99Updated last week
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆32Updated 2 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆67Updated last year
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆74Updated last week
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• JamesAslan / MicroArchBench
  ☆74Updated 10 months ago
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆12Updated last year
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• kuczmmar / Runahead
  Running ahead of memory latency - Part II project
  ☆10Updated 2 years ago
• cry-daniel / Computer-Architecture-Learning
  ☆64Updated 2 years ago
• miaochenlu / learn_prefetcher
  hardware & software prefetcher
  ☆26Updated last year
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆37Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆156Updated this week
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 3 months ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• car3s / IPCP_ISCA2020
  Source codes for "Bouquet of Instruction Pointers"
  ☆17Updated 4 years ago
• dhschall / LLBP
  Branch predictor simulation framework for the Last-Level Branch Predictor
  ☆27Updated last year
• gem5 / gem5-resources
  The official repository for the gem5 resources sources.
  ☆73Updated last month
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆34Updated last year
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated this week
• CMU-SAFARI / Virtuoso
  Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…
  ☆71Updated 4 months ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆20Updated 4 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 5 months ago
• bsc-mem / Mess-simulator
  A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.
  ☆26Updated last month
• gem5bootcamp / gem5-bootcamp-env
  The gem5 Bootcamp 2022 environment. Archived.
  ☆35Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• OpenXiangShan / gsim
  ☆53Updated 2 weeks ago