raghavrv / verilog
Simple Verilog Programs written for my VLSI coursework.
☆7Updated 11 years ago
Alternatives and similar repositories for verilog:
Users that are interested in verilog are comparing it to the libraries listed below
- Lecture about FIR filter on an FPGA☆12Updated 11 months ago
- opensource EDA tool flor VLSI design☆32Updated last year
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆125Updated 9 months ago
- 2014 UCSC Extension FPGA class☆13Updated 9 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 5 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆42Updated last year
- Design and implementation of a reconfigurable FIR filter in FPGA☆13Updated 2 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Updated 4 months ago
- Single Cycle RISC MIPS Processor☆32Updated 3 years ago
- UART implementation using verilog☆18Updated 2 years ago
- ☆15Updated 2 years ago
- This repo provide an index of VLSI content creators and their materials☆149Updated 8 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆85Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- ☆12Updated 3 weeks ago
- My HDL activities appear here. This is for my personal use. PPT's copyrights to University of Colorado Boulder.☆16Updated 4 years ago
- Implementing Different Adder Structures in Verilog☆65Updated 5 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆120Updated last year
- An 8 input interrupt controller written in Verilog.☆26Updated 13 years ago
- ☆16Updated 9 months ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆98Updated 4 years ago
- ☆17Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆75Updated last year
- 32 bit RISC-V CPU implementation in Verilog☆27Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆33Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆101Updated 11 months ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆110Updated 2 years ago
- RISC V core implementation using Verilog.☆26Updated 4 years ago
- ☆12Updated 5 months ago