sudhamshu091 / Hardware-Description-Languages-for-FPGA-Design
My HDL activities appear here. This is for my personal use. PPT's copyrights to University of Colorado Boulder.
☆14Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for Hardware-Description-Languages-for-FPGA-Design
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆34Updated 2 years ago
- ☆16Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated 2 years ago
- ☆10Updated 4 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.☆18Updated 2 years ago
- Lecture about FIR filter on an FPGA☆13Updated 6 months ago
- A compact, configurable RISC-V core☆11Updated last week
- ☆39Updated 2 years ago
- ☆26Updated 7 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year
- Verilog Fundamentals Explained for Beginners and Professionals☆18Updated last year
- Complete tutorial code.☆12Updated 6 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆12Updated last year
- opensource EDA tool flor VLSI design☆29Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆9Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- Architectural design of data router in verilog☆27Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆25Updated 9 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆34Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆20Updated 5 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆37Updated 3 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆12Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆22Updated 3 years ago
- ☆13Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆47Updated 2 weeks ago