Alternatives and similar repositories for Hardware-Description-Languages-for-FPGA-Design:

Users that are interested in Hardware-Description-Languages-for-FPGA-Design are comparing it to the libraries listed below

• semiDESIgner / 50daysRTLcode
  ☆16Updated last year
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆9Updated 5 months ago
• dineshannayya / riscduino_dcore
  ☆12Updated 6 months ago
• Marco-Winzker / FPGA-FIR-Filter
  Lecture about FIR filter on an FPGA
  ☆11Updated 8 months ago
• IEEE-NITK / VLSI_design-of-RISC
  IEEE Executive project for the year 2021-2022
  ☆8Updated 2 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆21Updated last year
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆14Updated 9 months ago
• vlsiexcellence / Digital-ASIC-Design-Projects-
  Verilog Design, Simulation & Synthesis of Digital ASIC Projects
  ☆13Updated 2 years ago
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆16Updated last year
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆28Updated 5 years ago
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆28Updated 2 years ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆36Updated 3 years ago
• yathAg / openroad_vsd_7nmContest
  ☆12Updated last year
• vlsiexcellence / Verilog-Crash-Course
  Verilog Fundamentals Explained for Beginners and Professionals
  ☆20Updated 2 years ago
• vsdip / vsdsram_sky130
  ☆40Updated 2 years ago
• kerimturak / tcore-rv32imc
  ☆11Updated this week
• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆24Updated 3 years ago
• shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…
  ☆41Updated 3 years ago
• IUST-Computer-Organization / LUMOS
  Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
  ☆48Updated 3 weeks ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆31Updated last year
• ishfaqahmed29 / FIFO_UVM_Verification
  Synchronous FIFO Testbench
  ☆10Updated 2 years ago
• aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130
  This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…
  ☆14Updated 3 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆19Updated 10 months ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆13Updated last year
• arunkpv / vsd-hdp
  ☆15Updated 6 months ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆51Updated 2 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆60Updated 5 years ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated this week
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆32Updated 2 years ago
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆15Updated 9 months ago