Alternatives and similar repositories for polarfire-soc-bare-metal-examples

Users that are interested in polarfire-soc-bare-metal-examples are comparing it to the libraries listed below

• polarfire-soc / polarfire-soc-documentation
  PolarFire SoC Documentation
  ☆59Updated 3 months ago
• polarfire-soc / hart-software-services
  PolarFire SoC hart software services
  ☆47Updated 2 months ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 7 months ago
• polarfire-soc / icicle-kit-reference-design
  PolarFire SoC Icicle Kit Libero reference design
  ☆42Updated 3 months ago
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆62Updated 7 months ago
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆84Updated this week
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆68Updated last month
• polarfire-soc / meta-polarfire-soc-yocto-bsp
  This repository is no longer maintained and will be archived, please see https://github.com/linux4microchip/meta-mchp
  ☆58Updated 3 months ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆69Updated 10 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆107Updated last month
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 5 months ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 3 months ago
• antmicro / renode-verilator-integration
  This repository contains sample code integrating Renode with Verilator
  ☆23Updated 5 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• filmil / vivado-docker
  Docker installation of Vivado tooling
  ☆26Updated 2 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆38Updated this week
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆110Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆91Updated 3 weeks ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆49Updated 2 weeks ago
• AEW2015 / fpga-colab
  FPGA examples on Google Colab
  ☆27Updated 2 months ago
• polarfire-soc / polarfire-soc-linux-examples
  ☆16Updated 3 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆86Updated 10 months ago
• antmicro / litex-vexriscv-tensorflow-lite-demo
  TF Lite demo on LiteX/VexRiscv soft RISC-V SoC on a Digilent Arty board
  ☆68Updated 3 years ago
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆97Updated 4 months ago
• vfinotti / cortex-m0-soft-microcontroller
  Soft-microcontroller implementation of an ARM Cortex-M0
  ☆26Updated 6 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆61Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 5 months ago
• lowRISC / sonata-system
  A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
  ☆46Updated last month
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆27Updated 6 years ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆163Updated last week