Alternatives and similar repositories for icicle-kit-reference-design:

Users that are interested in icicle-kit-reference-design are comparing it to the libraries listed below

• polarfire-soc / polarfire-soc-documentation
  PolarFire SoC Documentation
  ☆54Updated 3 weeks ago
• polarfire-soc / polarfire-soc-linux-examples
  ☆16Updated 3 weeks ago
• polarfire-soc / polarfire-soc-bare-metal-library
  Bare metal embedded software drivers and examples for PolarFire SoC
  ☆22Updated 3 years ago
• polarfire-soc / polarfire-soc-bare-metal-examples
  Bare metal example software projects for PolarFire SoC
  ☆34Updated last month
• polarfire-soc / hart-software-services
  PolarFire SoC hart software services
  ☆40Updated 3 weeks ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆48Updated last month
• open-design / riscv-soc-cores
  ☆37Updated 4 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• SpinalHDL / VexRiscvSocSoftware
  ☆27Updated 3 years ago
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆42Updated 2 years ago
• efard / DSPHDL
  ☆41Updated last year
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago
• polarfire-soc / meta-polarfire-soc-yocto-bsp
  PolarFire SoC yocto Board Support Package
  ☆54Updated 2 weeks ago
• nematoli / SPI-FPGA-VHDL
  SPI Master and Slave components to be used in all of FPGAs, written in VHDL.
  ☆36Updated 5 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆60Updated this week
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆50Updated 3 months ago
• bggardner / can-lite-vhdl
  A lightweight Controller Area Network (CAN) controller in VHDL
  ☆26Updated 5 months ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆67Updated 7 years ago
• stnolting / riscv-debug-dtm
  🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
  ☆26Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last month
• rodrigomelo9 / FOSS-for-FPGAs
  A getting started presentation (with examples) about how to use FLOSS for FPGA development.
  ☆35Updated last year
• mattvenn / gtkwave-python-filter-process
  ☆33Updated 4 years ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆18Updated 5 years ago
• Digilent / digilent-vivado-scripts
  ☆69Updated last month
• aesc-silicon / i2c-gpio-expander
  End-to-End Open-Source I2C GPIO Expander
  ☆31Updated last month
• MorrisMA / 1PPS-DPLL
  DPLL for phase-locking to 1PPS signal
  ☆31Updated 8 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆73Updated 2 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• openXC7 / demo-projects
  Demo projects for various Kintex FPGA boards
  ☆53Updated 10 months ago