Alternatives and similar repositories for polarfire-soc-linux-examples:

Users that are interested in polarfire-soc-linux-examples are comparing it to the libraries listed below

• polarfire-soc / polarfire-soc-documentation
  PolarFire SoC Documentation
  ☆54Updated last week
• polarfire-soc / icicle-kit-reference-design
  PolarFire SoC Icicle Kit Libero reference design
  ☆39Updated 3 weeks ago
• polarfire-soc / polarfire-soc-bare-metal-library
  Bare metal embedded software drivers and examples for PolarFire SoC
  ☆22Updated 3 years ago
• polarfire-soc / hart-software-services
  PolarFire SoC hart software services
  ☆40Updated 3 weeks ago
• polarfire-soc / polarfire-soc-bare-metal-examples
  Bare metal example software projects for PolarFire SoC
  ☆34Updated last month
• olofk / observer
  ☆41Updated 4 years ago
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆42Updated 2 years ago
• polarfire-soc / meta-polarfire-soc-yocto-bsp
  PolarFire SoC yocto Board Support Package
  ☆54Updated 3 weeks ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆31Updated 4 years ago
• nathanrossi / meta-hdl
  HDL tools layer for OpenEmbedded
  ☆17Updated 6 months ago
• antmicro / embench-tester
  ☆13Updated last year
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated last month
• openXC7 / xc7k325t-blinky-nextpnr
  ☆45Updated 2 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated 3 months ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆41Updated this week
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆49Updated last month
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆36Updated 2 years ago
• AEW2015 / fpga-colab
  FPGA examples on Google Colab
  ☆22Updated last year
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆50Updated 3 months ago
• gatecat / TrellisBoard
  Ultimate ECP5 development board
  ☆105Updated 5 years ago
• Xilinx / bootgen
  bootgen source code
  ☆42Updated 5 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆44Updated last week
• freecores / freecores.github.io
  Freecores website
  ☆19Updated 8 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• enjoy-digital / litex_vexriscv_smp_test
  VexRiscv-SMP integration test with LiteX.
  ☆25Updated 4 years ago
• controlpaths / litefury_rp5
  Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1
  ☆28Updated last year
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year