polarfire-soc / polarfire-soc-linux-examples
☆15Updated this week
Alternatives and similar repositories for polarfire-soc-linux-examples:
Users that are interested in polarfire-soc-linux-examples are comparing it to the libraries listed below
- PolarFire SoC Documentation☆52Updated 2 months ago
- Bare metal embedded software drivers and examples for PolarFire SoC☆22Updated 3 years ago
- PolarFire SoC Icicle Kit Libero reference design☆38Updated last month
- PolarFire SoC hart software services☆37Updated 3 months ago
- ☆41Updated 4 years ago
- Bare metal example software projects for PolarFire SoC☆34Updated this week
- Small footprint and configurable JESD204B core☆41Updated 2 months ago
- VexRiscv-SMP integration test with LiteX.☆25Updated 4 years ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- Spen's Official OpenOCD Mirror☆48Updated this week
- PolarFire SoC yocto Board Support Package☆52Updated 5 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆31Updated 2 weeks ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆28Updated 2 years ago
- ☆45Updated 2 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- ☆13Updated last year
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆55Updated 2 weeks ago
- Siglent SDS1x0xX-E FPGA bitstreams☆40Updated 2 months ago
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆26Updated 2 years ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆42Updated 2 years ago
- Tiny tips for Colorlight i5 FPGA board☆56Updated 3 years ago
- FPGA board-level debugging and reverse-engineering tool☆36Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Small footprint and configurable SPI core☆41Updated 2 months ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆38Updated 2 months ago
- I want to learn [n]Migen.☆40Updated 5 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆43Updated this week
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago