antmicro / litex-vexriscv-tensorflow-lite-demoLinks
TF Lite demo on LiteX/VexRiscv soft RISC-V SoC on a Digilent Arty board
☆68Updated 3 years ago
Alternatives and similar repositories for litex-vexriscv-tensorflow-lite-demo
Users that are interested in litex-vexriscv-tensorflow-lite-demo are comparing it to the libraries listed below
Sorting:
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- tinyVision.ai Vision & Sensor FPGA System on Module☆45Updated 4 years ago
- ☆63Updated 6 years ago
- Spen's Official OpenOCD Mirror☆50Updated 7 months ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆125Updated 5 months ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- FuseSoC standard core library☆147Updated 5 months ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 5 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 4 months ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆91Updated 9 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated 3 weeks ago
- ☆42Updated 5 years ago
- Naive Educational RISC V processor☆91Updated 2 weeks ago
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- FPGA tool performance profiling☆102Updated last year
- FOS - FPGA Operating System☆73Updated 5 years ago
- Small footprint and configurable SPI core☆45Updated 2 weeks ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆62Updated 7 months ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆110Updated last year
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- A Python package to use FPGA development tools programmatically.☆140Updated 7 months ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆21Updated 5 years ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆63Updated 2 weeks ago