Alternatives and similar repositories for legv8

Users that are interested in legv8 are comparing it to the libraries listed below

• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆95Updated 5 years ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆140Updated 2 years ago
• grantae / OpenMIPS
  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions,…
  ☆83Updated 6 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated last week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆199Updated this week
• larkmjc / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆101Updated 3 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆153Updated last year
• esmil / riscv-linux
  Getting started running RISC-V Linux
  ☆18Updated 4 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆108Updated 4 years ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆52Updated 4 years ago
• johnwinans / rvddt
  RISC-V Dynamic Debugging Tool
  ☆52Updated 2 years ago
• racerxdl / riscv-online-asm
  RISC-V Online Assembler using Emscripten, Gnu Binutils
  ☆63Updated 2 years ago
• nxbyte / ARM-LEGv8
  Verilog Implementation of an ARM LEGv8 CPU
  ☆111Updated 7 years ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆283Updated this week
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆150Updated 3 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆63Updated 2 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆79Updated 3 years ago
• pulp-platform / pulp-freertos
  FreeRTOS for PULP
  ☆16Updated 2 years ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆172Updated 5 years ago
• merledu / SIngle-Cycle-RISC-V-In-Verilog
  This repository contains the verilog code files of Single Cycle RISC-V architecture
  ☆39Updated 6 years ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• openhwgroup / corev-gcc
  ☆26Updated last year
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆202Updated last year
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆64Updated last year
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆74Updated 11 years ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆76Updated last month
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆252Updated last year
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆57Updated 2 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• riscv-software-src / riscv-config
  RISC-V Configuration Validator
  ☆80Updated 9 months ago