Alternatives and similar repositories for legv8

Users that are interested in legv8 are comparing it to the libraries listed below

• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆145Updated 6 months ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆46Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆97Updated 3 years ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆91Updated 2 weeks ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• ucb-bar / testchipip
  ☆84Updated last week
• riscv / riscv-test-env
  ☆46Updated last week
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆55Updated 6 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆89Updated 5 years ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆98Updated 2 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆235Updated 6 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆88Updated 4 years ago
• hughperkins / cpu-tutorial
  Tutorial on building your own CPU, in Verilog
  ☆33Updated 3 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 2 months ago
• riscv-software-src / riscv-config
  RISC-V Configuration Validator
  ☆79Updated last month
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆63Updated 6 years ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆48Updated 8 months ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆167Updated 4 years ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆135Updated 2 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆82Updated 4 years ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆183Updated 2 weeks ago
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆33Updated last year
• grantae / OpenMIPS
  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions,…
  ☆73Updated 5 years ago
• riscvarchive / riscv-newlib
  RISC-V port of newlib
  ☆97Updated 3 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last week