Alternatives and similar repositories for legv8

Users that are interested in legv8 are comparing it to the libraries listed below

• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆95Updated 5 years ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆54Updated 4 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated last week
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆142Updated 2 years ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆60Updated 2 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆65Updated 8 months ago
• grantae / OpenMIPS
  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions,…
  ☆83Updated 6 years ago
• freecores / mcs-4
  4004 CPU and MCS-4 family chips
  ☆44Updated 11 years ago
• lupyuen / nuttx-star64
  Apache NuttX RTOS for Pine64 Star64 64-bit RISC-V SBC (StarFive JH7110)
  ☆32Updated this week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆154Updated last year
• cpantel / DVGHV
  Designing Video Game Hardware in Verilog
  ☆27Updated 6 years ago
• johnwinans / rvalp
  RISC-V Assembly Language Programming
  ☆244Updated last month
• riscv-admin / riscv-ovpsim
  ☆62Updated 5 years ago
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆75Updated 11 years ago
• arm-university / Graphical-Micro-Architecture-Simulator
  Graphical-Micro-Architecture-Simulator
  ☆123Updated 7 months ago
• johnwinans / riscv-toolchain-install-guide
  How to download & install qemu a toolchain suitable for building and running freestanding RISC-V C/C++ programs
  ☆59Updated last year
• noteed / riscv-hello-c
  Bare metal RISC-V hello world in C
  ☆20Updated 6 years ago
• johnwinans / rvddt
  RISC-V Dynamic Debugging Tool
  ☆52Updated 2 years ago
• esmil / riscv-linux
  Getting started running RISC-V Linux
  ☆18Updated 4 years ago
• antmicro / renode-verilator-integration
  This repository contains sample code integrating Renode with Verilator
  ☆26Updated 8 months ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆79Updated 3 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆63Updated 2 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆35Updated 2 years ago
• racerxdl / riscv-online-asm
  RISC-V Online Assembler using Emscripten, Gnu Binutils
  ☆63Updated 2 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆109Updated 4 years ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆158Updated last month
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆172Updated 5 years ago
• pulp-platform / pulp-freertos
  FreeRTOS for PULP
  ☆16Updated 2 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆64Updated last year
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆205Updated this week