Alternatives and similar repositories for legv8:

Users that are interested in legv8 are comparing it to the libraries listed below

• stnolting / neorv32-riscof
  ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆30Updated this week
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆65Updated this week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 5 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆138Updated 2 months ago
• thinkoco / de10-nano-riscv
  A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
  ☆34Updated 4 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆48Updated 10 months ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆45Updated 4 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆29Updated 8 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 7 months ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆83Updated 4 months ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆84Updated 5 years ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆45Updated 8 months ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆39Updated this week
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• sifive / elf2hex
  Converts ELF files to HEX files that are suitable for Verilog's readmemh.
  ☆83Updated 2 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆58Updated 6 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆56Updated this week
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆132Updated last year
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆25Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆93Updated 3 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆54Updated 3 years ago
• ucb-bar / testchipip
  ☆82Updated last week
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆49Updated 5 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆60Updated last month
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆153Updated 4 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆42Updated 2 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆64Updated 9 months ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago