Alternatives and similar repositories for Genesys-ZU

Users that are interested in Genesys-ZU are comparing it to the libraries listed below

• ATaylorCEngFIET / Xilinx_BootCamp
  Slides and material for Xilinx bootcamp
  ☆22Updated 4 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆63Updated 10 months ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 2 months ago
• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆112Updated last year
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆33Updated 2 weeks ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆95Updated this week
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆50Updated 2 years ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆156Updated last year
• HDLForBeginners / Examples
  ☆104Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆80Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 2 months ago
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆83Updated this week
• Avnet / bdf
  Avnet Board Definition Files
  ☆134Updated last week
• ATaylorCEngFIET / Vitis_Hero
  ☆28Updated 3 years ago
• sifferman / fusesoc_template
  Example of how to get started with olofk/fusesoc.
  ☆17Updated 4 years ago
• tomverbeure / kv260_bringup
  Temporary repo to gather information about the Kria KV260 board
  ☆72Updated 4 years ago
• MakarenaLabs / Common-PL-Devices-on-PYNQ
  Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)
  ☆38Updated 4 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆106Updated 3 weeks ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• efard / DSPHDL
  Digital Signal Processing and Well-Known Modulations on HDL
  ☆41Updated 4 months ago
• Xilinx / XilinxCEDStore
  This store contains Configurable Example Designs.
  ☆50Updated 2 weeks ago
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆121Updated this week
• aesc-silicon / i2c-gpio-expander
  End-to-End Open-Source I2C GPIO Expander
  ☆33Updated 2 months ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆113Updated 10 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆66Updated last week
• Xilinx / Xilinx_Kria_KV260_Workshop
  ☆47Updated 4 years ago
• viktor-nikolov / MicroBlaze-DDR3-tutorial
  Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
  ☆56Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 2 months ago