Alternatives and similar repositories for Genesys-ZU

Users that are interested in Genesys-ZU are comparing it to the libraries listed below

• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆120Updated last year
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆74Updated last year
• Digilent / axi4lite_ip_gen
  Generates simple AXI4-lite IP for use in Vivado from register specifications
  ☆15Updated 9 months ago
• Xilinx / Xilinx_Kria_KV260_Workshop
  ☆50Updated 4 years ago
• Digilent / digilent-vivado-scripts
  ☆70Updated 5 months ago
• ATaylorCEngFIET / Xilinx_BootCamp
  Slides and material for Xilinx bootcamp
  ☆22Updated 4 years ago
• tomverbeure / kv260_bringup
  Temporary repo to gather information about the Kria KV260 board
  ☆74Updated 4 years ago
• HDLForBeginners / Examples
  ☆115Updated 2 years ago
• ATaylorCEngFIET / Vitis_Hero
  ☆29Updated 3 years ago
• antmicro / kria-k26-devboard
  Open source AMD Xilinx Kria UltraScale+ SoM baseboard
  ☆63Updated 11 months ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆43Updated 2 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆65Updated last year
• Xilinx / Embedded-Design-Tutorials
  ☆154Updated this week
• irmo-de / xilinx-risc-v
  Porting PicoRV32 to Artix-7 and Spartan-7. Generic vivado template for supported Xilinx FPGA is included.
  ☆45Updated last year
• viktor-nikolov / MicroBlaze-DDR3-tutorial
  Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
  ☆68Updated last month
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated 2 years ago
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆63Updated 9 months ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆159Updated last year
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆85Updated 2 years ago
• TinyTapeout / tt-support-tools
  Tiny Tapeout project build tools + chip integration scripts
  ☆28Updated 3 weeks ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆51Updated 3 years ago
• Avnet / ZUBoard_1CG-PYNQ
  ☆19Updated 3 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆101Updated last month
• k0nze / zedboard_axi4_master_burst_example
  Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)
  ☆44Updated 8 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆72Updated 8 years ago
• opalkelly-opensource / design-resources
  A collection of Opal Kelly provided design resources
  ☆17Updated 2 months ago
• Digilent / embeddedsw
  Xilinx Embedded Software (embeddedsw) Development
  ☆13Updated 7 months ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆120Updated last year
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆169Updated 4 years ago
• gtaylormb / ultra96v2_imx219_to_displayport
  Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL
  ☆74Updated 3 years ago