Alternatives and similar repositories for wishbone

Users that are interested in wishbone are comparing it to the libraries listed below

• mattvenn / caravel_user_project
  Zero to ASIC group submission for MPW2
  ☆13Updated last month
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆25Updated 2 months ago
• BBN-Q / VHDL-FIR-filters
  Synthesizable FIR filters in VHDL
  ☆14Updated 5 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆22Updated 3 months ago
• salcanmor / SRAM-tester-for-Cmod-A7-35T
  Tester for IS61WV5128BLL-10BLI SRAM in Cmod A7-35T
  ☆18Updated 6 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆23Updated 10 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆34Updated 7 years ago
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆13Updated 7 months ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• ChrisPVille / mig_example
  Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
  ☆31Updated 2 years ago
• tinylabs / tinylabs-cores
  Fusesoc compatible rtl cores
  ☆15Updated 2 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆41Updated 4 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆32Updated 4 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆21Updated last year
• BrianHGinc / Verilog-Floating-Point-Clock-Divider
  Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…
  ☆19Updated 3 months ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆54Updated 5 months ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 5 months ago
• Cognoscan / BoostDSP
  VHDL Library for implementing common DSP functionality.
  ☆27Updated 6 years ago
• AngeloJacobo / FPGA_SDRAM_Controller
  SDRAM controller optimized to a memory bandwidth of 316MB/s
  ☆26Updated 3 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆45Updated 2 years ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• wnew / hdl_library
  A library of verilog and vhdl modules
  ☆15Updated 6 years ago
• ldoolitt / vhd2vl
  ☆132Updated 5 months ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 6 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆10Updated 2 years ago