Alternatives and similar repositories for UVM

Users that are interested in UVM are comparing it to the libraries listed below

• Suntrakanesh / System-Verilog-bootcamp
  System Verilog BootCamp
  ☆25Updated 3 years ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆37Updated 3 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆93Updated last year
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆48Updated 2 years ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆126Updated 3 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆42Updated last year
• mbits-mirafra / SystemVerilogCourse
  This is a detailed SystemVerilog course
  ☆129Updated 9 months ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆76Updated 6 years ago
• psnjk / SimpleCache
  Simple cache design implementation in verilog
  ☆55Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆64Updated last year
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆115Updated 5 years ago
• vlsiexcellence / Static-Timing-Analysis-Full-Course
  Static Timing Analysis Full Course
  ☆63Updated 2 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆73Updated 4 years ago
• AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
  This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…
  ☆58Updated 2 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆159Updated 3 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆51Updated 6 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆161Updated 3 years ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆129Updated 3 years ago
• raysalemi / Python4RTLVerification
  ☆170Updated 3 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 5 months ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆37Updated 9 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 4 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆77Updated 5 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆26Updated 2 years ago
• somyadashora / AMBA-AXI4-Lite
  Master and Slave made using AMBA AXI4 Lite protocol.
  ☆29Updated 5 years ago
• mbits-mirafra / UVMCourse
  Structured UVM Course
  ☆54Updated last year
• karribharathi / 100-Days-of-RTL
  ☆17Updated last year
• shubhi704 / APB-Protocol
  ☆52Updated 4 years ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆46Updated 4 years ago