Alternatives and similar repositories for tcc-riscv32

Users that are interested in tcc-riscv32 are comparing it to the libraries listed below

• mausimus / rvcc
  Standalone C compiler for RISC-V and ARM
  ☆88Updated last year
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆53Updated 4 years ago
• ultraembedded / fat_io_lib
  Small footprint, low dependency, C code implementation of a FAT16 & FAT32 driver.
  ☆68Updated 6 years ago
• AntonMause / rv16poc
  16 bit RISC-V proof of concept
  ☆24Updated 10 months ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆61Updated 2 months ago
• jevinskie / riscv-smol-linux-kernel
  Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM
  ☆24Updated 2 years ago
• howerj / bit-serial
  A bit-serial CPU written in VHDL, with a simulator written in C.
  ☆128Updated 11 months ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 2 weeks ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆53Updated 2 years ago
• b-dmitry1 / V188
  FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)
  ☆23Updated 3 years ago
• franzflasch / riscv_em
  Simple risc-v emulator, able to run linux, written in C.
  ☆142Updated last year
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆50Updated 2 years ago
• smunaut / doom_riscv
  Doom classic port to lightweight RISC‑V
  ☆94Updated 3 years ago
• krakenlake / vmon
  Tiny RISC-V machine code monitor written in RISC-V assembly.
  ☆47Updated last week
• JulianKemmerer / PipelineC-Graphics
  Graphics demos
  ☆110Updated last year
• regymm / buildroot
  buildroot fork from damien -- RV32 no MMU Linux. Run "make qemu_riscv32_nommu_virt_minimal_defconfig" then "make"
  ☆26Updated last year
• theandrew168 / bronzebeard
  Minimal assembler and ecosystem for bare-metal RISC-V development
  ☆53Updated last year
• howerj / lfsr-vhdl
  An implementation of a CPU that uses a Linear Feedback Shift Register as a Program Counter instead of a normal one
  ☆52Updated last month
• Chalandi / Blinky_Pico2_dual_core_nosdk
  Bare-metal programming on RP2350 dual-core ARM Cortex-m33/RISC-V Hazard3 (non-SDK)
  ☆18Updated 2 months ago
• suarezvictor / CflexHDL
  Design digital circuits in C. Simulate really fast with a regular compiler.
  ☆174Updated 2 years ago
• YoWASP / vscode
  YoWASP toolchain for Visual Studio Code
  ☆20Updated 3 weeks ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆38Updated 4 years ago
• lupyuen / tcc-riscv32-wasm
  TCC (Tiny C Compiler) for 64-bit RISC-V, compiled to WebAssembly with Zig Compiler
  ☆44Updated last year
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆31Updated 2 years ago
• nsauzede / cpu86
  🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA
  ☆45Updated 7 months ago
• pineapple-one / logisim-simulation
  Simulation in Logisim-Evolution HC
  ☆34Updated 4 years ago
• osresearch / risc8
  Mostly AVR compatible FPGA soft-core
  ☆28Updated 3 years ago
• BrunoLevy / TinyPrograms
  Tiny programs from various sources, for testing softcores
  ☆117Updated 6 months ago
• popovicu / linux-no-mmu-userspace-example
  ☆41Updated last year
• racerxdl / riscv-online-asm
  RISC-V Online Assembler using Emscripten, Gnu Binutils
  ☆56Updated last year